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xHCI: Clear PLC for USB2 root hub ports

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When the link state changes, xHC will report a port status change event
and set the PORT_PLC bit, for both USB3 and USB2 root hub ports.

The PLC will be cleared by usbcore for USB3 root hub ports, but not for
USB2 ports, because they do not report USB_PORT_STAT_C_LINK_STATE in
wPortChange.

Clear it for USB2 root hub ports in handle_port_status().

Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Andiry Xu 2011-09-23 14:19:50 -07:00 committed by Greg Kroah-Hartman
parent d2f52c9e58
commit 6fd4562178
1 changed files with 4 additions and 0 deletions
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4
drivers/usb/host/xhci-ring.c
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@ -1352,6 +1352,10 @@ static void handle_port_status(struct xhci_hcd *xhci,
}
}
if (hcd->speed != HCD_USB3)
xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
PORT_PLC);
cleanup:
/* Update event ring dequeue pointer before dropping the lock */
inc_deq(xhci, xhci->event_ring, true);