[POWERPC] celleb: Consolidate io-workarounds code
Now, we can use generic io-workarounds mechanism and the workaround code for spider-pci. This changes Celleb PCI code to use spider-pci code. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Ishizaki Kou
Paul Mackerras
parent
7cfb62a2e8
commit
6ec859e1b2
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@ -27,3 +27,9 @@ obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \
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spufs/
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obj-$(CONFIG_PCI_MSI) += axon_msi.o
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# celleb stuff
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ifeq ($(CONFIG_PPC_CELLEB),y)
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obj-y += io-workarounds.o spider-pci.o
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endif
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@ -1,7 +1,6 @@
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obj-y += interrupt.o iommu.o setup.o \
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htab.o beat.o hvCall.o pci.o \
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scc_epci.o scc_uhc.o \
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io-workarounds.o
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scc_epci.o scc_uhc.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_PPC_UDBG_BEAT) += udbg_beat.o
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@ -1,280 +0,0 @@
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/*
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* Support for Celleb io workarounds
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This file is based to arch/powerpc/platform/cell/io-workarounds.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include "pci.h"
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#define MAX_CELLEB_PCI_BUS 4
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void *celleb_dummy_page_va;
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static struct celleb_pci_bus {
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struct pci_controller *phb;
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void (*dummy_read)(struct pci_controller *);
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} celleb_pci_busses[MAX_CELLEB_PCI_BUS];
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static int celleb_pci_count = 0;
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static struct celleb_pci_bus *celleb_pci_find(unsigned long vaddr,
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unsigned long paddr)
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{
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int i, j;
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struct resource *res;
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for (i = 0; i < celleb_pci_count; i++) {
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struct celleb_pci_bus *bus = &celleb_pci_busses[i];
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struct pci_controller *phb = bus->phb;
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if (paddr)
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for (j = 0; j < 3; j++) {
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res = &phb->mem_resources[j];
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if (paddr >= res->start && paddr <= res->end)
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return bus;
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}
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res = &phb->io_resource;
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if (vaddr && vaddr >= res->start && vaddr <= res->end)
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return bus;
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}
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return NULL;
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}
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static void celleb_io_flush(const PCI_IO_ADDR addr)
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{
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struct celleb_pci_bus *bus;
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int token;
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token = PCI_GET_ADDR_TOKEN(addr);
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if (token && token <= celleb_pci_count)
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bus = &celleb_pci_busses[token - 1];
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else {
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unsigned long vaddr, paddr;
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pte_t *ptep;
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vaddr = (unsigned long)PCI_FIX_ADDR(addr);
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if (vaddr < PHB_IO_BASE || vaddr >= PHB_IO_END)
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return;
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ptep = find_linux_pte(init_mm.pgd, vaddr);
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if (ptep == NULL)
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paddr = 0;
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else
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paddr = pte_pfn(*ptep) << PAGE_SHIFT;
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bus = celleb_pci_find(vaddr, paddr);
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if (bus == NULL)
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return;
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}
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if (bus->dummy_read)
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bus->dummy_read(bus->phb);
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}
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static u8 celleb_readb(const PCI_IO_ADDR addr)
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{
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u8 val;
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val = __do_readb(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u16 celleb_readw(const PCI_IO_ADDR addr)
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{
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u16 val;
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val = __do_readw(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u32 celleb_readl(const PCI_IO_ADDR addr)
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{
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u32 val;
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val = __do_readl(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u64 celleb_readq(const PCI_IO_ADDR addr)
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{
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u64 val;
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val = __do_readq(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u16 celleb_readw_be(const PCI_IO_ADDR addr)
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{
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u16 val;
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val = __do_readw_be(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u32 celleb_readl_be(const PCI_IO_ADDR addr)
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{
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u32 val;
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val = __do_readl_be(addr);
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celleb_io_flush(addr);
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return val;
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}
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static u64 celleb_readq_be(const PCI_IO_ADDR addr)
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{
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u64 val;
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val = __do_readq_be(addr);
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celleb_io_flush(addr);
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return val;
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}
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static void celleb_readsb(const PCI_IO_ADDR addr,
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void *buf, unsigned long count)
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{
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__do_readsb(addr, buf, count);
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celleb_io_flush(addr);
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}
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static void celleb_readsw(const PCI_IO_ADDR addr,
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void *buf, unsigned long count)
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{
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__do_readsw(addr, buf, count);
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celleb_io_flush(addr);
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}
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static void celleb_readsl(const PCI_IO_ADDR addr,
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void *buf, unsigned long count)
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{
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__do_readsl(addr, buf, count);
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celleb_io_flush(addr);
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}
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static void celleb_memcpy_fromio(void *dest,
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const PCI_IO_ADDR src,
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unsigned long n)
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{
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__do_memcpy_fromio(dest, src, n);
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celleb_io_flush(src);
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}
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static void __iomem *celleb_ioremap(unsigned long addr,
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unsigned long size,
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unsigned long flags)
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{
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struct celleb_pci_bus *bus;
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void __iomem *res = __ioremap(addr, size, flags);
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int busno;
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bus = celleb_pci_find(0, addr);
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if (bus != NULL) {
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busno = bus - celleb_pci_busses;
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PCI_SET_ADDR_TOKEN(res, busno + 1);
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}
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return res;
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}
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static void celleb_iounmap(volatile void __iomem *addr)
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{
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return __iounmap(PCI_FIX_ADDR(addr));
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}
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static struct ppc_pci_io celleb_pci_io __initdata = {
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.readb = celleb_readb,
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.readw = celleb_readw,
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.readl = celleb_readl,
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.readq = celleb_readq,
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.readw_be = celleb_readw_be,
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.readl_be = celleb_readl_be,
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.readq_be = celleb_readq_be,
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.readsb = celleb_readsb,
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.readsw = celleb_readsw,
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.readsl = celleb_readsl,
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.memcpy_fromio = celleb_memcpy_fromio,
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};
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void __init celleb_pci_add_one(struct pci_controller *phb,
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void (*dummy_read)(struct pci_controller *))
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{
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struct celleb_pci_bus *bus = &celleb_pci_busses[celleb_pci_count];
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struct device_node *np = phb->dn;
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if (celleb_pci_count >= MAX_CELLEB_PCI_BUS) {
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printk(KERN_ERR "Too many pci bridges, workarounds"
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" disabled for %s\n", np->full_name);
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return;
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}
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celleb_pci_count++;
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bus->phb = phb;
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bus->dummy_read = dummy_read;
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}
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static struct of_device_id celleb_pci_workaround_match[] __initdata = {
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{
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.name = "pci-pseudo",
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.data = fake_pci_workaround_init,
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}, {
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.name = "epci",
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.data = epci_workaround_init,
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}, {
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},
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};
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int __init celleb_pci_workaround_init(void)
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{
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struct pci_controller *phb;
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struct device_node *node;
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const struct of_device_id *match;
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void (*init_func)(struct pci_controller *);
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celleb_dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!celleb_dummy_page_va) {
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printk(KERN_ERR "Celleb: dummy read disabled. "
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"Alloc celleb_dummy_page_va failed\n");
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return 1;
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}
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list_for_each_entry(phb, &hose_list, list_node) {
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node = phb->dn;
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match = of_match_node(celleb_pci_workaround_match, node);
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if (match) {
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init_func = match->data;
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(*init_func)(phb);
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}
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}
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ppc_pci_io = celleb_pci_io;
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ppc_md.ioremap = celleb_ioremap;
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ppc_md.iounmap = celleb_iounmap;
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return 0;
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}
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@ -41,6 +41,7 @@
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include "../cell/io-workarounds.h"
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#include "pci.h"
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#include "interrupt.h"
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@ -457,33 +458,39 @@ static int __init celleb_setup_fake_pci(struct device_node *dev,
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return 0;
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}
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void __init fake_pci_workaround_init(struct pci_controller *phb)
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{
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/**
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* We will add fake pci bus to scc_pci_bus for the purpose to improve
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* I/O Macro performance. But device-tree and device drivers
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* are not ready to use address with a token.
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*/
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/* celleb_pci_add_one(phb, NULL); */
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}
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static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
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.setup = celleb_setup_fake_pci,
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};
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static struct of_device_id celleb_phb_match[] __initdata = {
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{
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.name = "pci-pseudo",
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.data = celleb_setup_fake_pci,
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.data = &celleb_fake_pci_spec,
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}, {
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.name = "epci",
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.data = celleb_setup_epci,
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.data = &celleb_epci_spec,
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}, {
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},
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};
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static int __init celleb_io_workaround_init(struct pci_controller *phb,
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struct celleb_phb_spec *phb_spec)
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{
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if (phb_spec->ops) {
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iowa_register_bus(phb, phb_spec->ops, phb_spec->iowa_init,
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phb_spec->iowa_data);
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io_workaround_init();
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}
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return 0;
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}
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int __init celleb_setup_phb(struct pci_controller *phb)
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{
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struct device_node *dev = phb->dn;
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const struct of_device_id *match;
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int (*setup_func)(struct device_node *, struct pci_controller *);
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struct celleb_phb_spec *phb_spec;
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int rc;
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match = of_match_node(celleb_phb_match, dev);
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if (!match)
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@ -492,8 +499,12 @@ int __init celleb_setup_phb(struct pci_controller *phb)
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phb_set_bus_ranges(dev, phb);
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phb->buid = 1;
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setup_func = match->data;
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return (*setup_func)(dev, phb);
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phb_spec = match->data;
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rc = (*phb_spec->setup)(dev, phb);
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if (rc)
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return 1;
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return celleb_io_workaround_init(phb, phb_spec);
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}
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int celleb_pci_probe_mode(struct pci_bus *bus)
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@ -27,16 +27,18 @@
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#include <asm/prom.h>
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#include <asm/ppc-pci.h>
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#include "../cell/io-workarounds.h"
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struct celleb_phb_spec {
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int (*setup)(struct device_node *, struct pci_controller *);
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struct ppc_pci_io *ops;
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int (*iowa_init)(struct iowa_bus *, void *);
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void *iowa_data;
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};
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extern int celleb_setup_phb(struct pci_controller *);
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extern int celleb_pci_probe_mode(struct pci_bus *);
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extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
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extern void *celleb_dummy_page_va;
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extern int __init celleb_pci_workaround_init(void);
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extern void __init celleb_pci_add_one(struct pci_controller *,
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void (*)(struct pci_controller *));
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extern void fake_pci_workaround_init(struct pci_controller *);
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extern void epci_workaround_init(struct pci_controller *);
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extern struct celleb_phb_spec celleb_epci_spec;
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#endif /* _CELLEB_PCI_H */
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@ -43,10 +43,6 @@
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#define iob() __asm__ __volatile__("eieio; sync":::"memory")
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struct epci_private {
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dma_addr_t dummy_page_da;
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};
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static inline PCI_IO_ADDR celleb_epci_get_epci_base(
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struct pci_controller *hose)
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{
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@ -71,42 +67,6 @@ static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
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return hose->cfg_data;
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}
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static void scc_epci_dummy_read(struct pci_controller *hose)
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{
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PCI_IO_ADDR epci_base;
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u32 val;
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epci_base = celleb_epci_get_epci_base(hose);
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val = in_be32(epci_base + SCC_EPCI_WATRP);
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iosync();
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return;
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}
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void __init epci_workaround_init(struct pci_controller *hose)
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{
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PCI_IO_ADDR epci_base;
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PCI_IO_ADDR reg;
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struct epci_private *private = hose->private_data;
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BUG_ON(!private);
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private->dummy_page_da = dma_map_single(hose->parent,
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celleb_dummy_page_va, PAGE_SIZE, DMA_FROM_DEVICE);
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if (private->dummy_page_da == DMA_ERROR_CODE) {
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printk(KERN_ERR "EPCI: dummy read disabled. "
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"Map dummy page failed.\n");
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return;
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}
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celleb_pci_add_one(hose, scc_epci_dummy_read);
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epci_base = celleb_epci_get_epci_base(hose);
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reg = epci_base + SCC_EPCI_DUMYRADR;
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out_be32(reg, private->dummy_page_da);
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}
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static inline void clear_and_disable_master_abort_interrupt(
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struct pci_controller *hose)
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{
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@ -425,8 +385,8 @@ static int __init celleb_epci_init(struct pci_controller *hose)
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return 0;
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}
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int __init celleb_setup_epci(struct device_node *node,
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struct pci_controller *hose)
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static int __init celleb_setup_epci(struct device_node *node,
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struct pci_controller *hose)
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{
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struct resource r;
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|
||||
|
|
@ -462,20 +422,12 @@ int __init celleb_setup_epci(struct device_node *node,
|
|||
r.start, (unsigned long)hose->cfg_data,
|
||||
(r.end - r.start + 1));
|
||||
|
||||
hose->private_data = kzalloc(sizeof(struct epci_private), GFP_KERNEL);
|
||||
if (hose->private_data == NULL) {
|
||||
printk(KERN_ERR "EPCI: no memory for private data.\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
hose->ops = &celleb_epci_ops;
|
||||
celleb_epci_init(hose);
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
kfree(hose->private_data);
|
||||
|
||||
if (hose->cfg_addr)
|
||||
iounmap(hose->cfg_addr);
|
||||
|
||||
|
|
@ -483,3 +435,10 @@ error:
|
|||
iounmap(hose->cfg_data);
|
||||
return 1;
|
||||
}
|
||||
|
||||
struct celleb_phb_spec celleb_epci_spec __initdata = {
|
||||
.setup = celleb_setup_epci,
|
||||
.ops = &spiderpci_ops,
|
||||
.iowa_init = &spiderpci_iowa_init,
|
||||
.iowa_data = (void *)0,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -114,8 +114,6 @@ static int __init celleb_publish_devices(void)
|
|||
/* Publish OF platform devices for southbridge IOs */
|
||||
of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
|
||||
|
||||
celleb_pci_workaround_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_device_initcall(celleb_beat, celleb_publish_devices);
|
||||
|
|
|
|||
Reference in New Issue