[ARM] 3429/1: ARM: OMAP: 4/8 Update GPIO
Patch from Tony Lindgren Update OMAP GPIO code from linux-omap tree: - Fix omap16xx edge control by Juha Yrjola - Support for additional omap16xx trigger modes by Dirk Behme - Fix edge detection by Tony Lindgren et al. - Better support for omap15xx and omap310 by Andrej Zaborowski - Fix omap15xx interrupt bug by Petukhov Nikolay Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
Russell King
parent
8d7f9f5037
commit
6e60e79a1d
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@ -174,7 +174,7 @@ static int gpio_bank_count;
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static inline struct gpio_bank *get_gpio_bank(int gpio)
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{
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap1510()) {
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if (cpu_is_omap15xx()) {
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if (OMAP_GPIO_IS_MPUIO(gpio))
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return &gpio_bank[0];
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return &gpio_bank[1];
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@ -223,7 +223,7 @@ static inline int gpio_valid(int gpio)
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return 0;
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}
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap1510() && gpio < 16)
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if (cpu_is_omap15xx() && gpio < 16)
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return 0;
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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@ -402,13 +402,13 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
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u32 gpio_bit = 1 << gpio;
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
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trigger & IRQT_LOW);
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trigger & __IRQT_LOWLVL);
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
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trigger & IRQT_HIGH);
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trigger & __IRQT_HIGHLVL);
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MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
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trigger & IRQT_RISING);
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trigger & __IRQT_RISEDGE);
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MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
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trigger & IRQT_FALLING);
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trigger & __IRQT_FALEDGE);
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/* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
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* triggering requested. */
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}
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@ -422,9 +422,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_INT_EDGE;
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l = __raw_readl(reg);
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if (trigger == IRQT_RISING)
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if (trigger & __IRQT_RISEDGE)
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l |= 1 << gpio;
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else if (trigger == IRQT_FALLING)
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else if (trigger & __IRQT_FALEDGE)
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l &= ~(1 << gpio);
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else
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goto bad;
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@ -432,9 +432,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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case METHOD_GPIO_1510:
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reg += OMAP1510_GPIO_INT_CONTROL;
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l = __raw_readl(reg);
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if (trigger == IRQT_RISING)
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if (trigger & __IRQT_RISEDGE)
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l |= 1 << gpio;
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else if (trigger == IRQT_FALLING)
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else if (trigger & __IRQT_FALEDGE)
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l &= ~(1 << gpio);
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else
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goto bad;
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@ -446,20 +446,21 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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reg += OMAP1610_GPIO_EDGE_CTRL1;
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gpio &= 0x07;
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/* We allow only edge triggering, i.e. two lowest bits */
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if (trigger & ~IRQT_BOTHEDGE)
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if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
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BUG();
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/* NOTE: knows __IRQT_{FAL,RIS}EDGE match OMAP hardware */
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trigger &= 0x03;
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l = __raw_readl(reg);
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l &= ~(3 << (gpio << 1));
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l |= trigger << (gpio << 1);
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if (trigger & __IRQT_RISEDGE)
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l |= 2 << (gpio << 1);
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if (trigger & __IRQT_FALEDGE)
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l |= 1 << (gpio << 1);
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break;
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case METHOD_GPIO_730:
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reg += OMAP730_GPIO_INT_CONTROL;
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l = __raw_readl(reg);
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if (trigger == IRQT_RISING)
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if (trigger & __IRQT_RISEDGE)
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l |= 1 << gpio;
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else if (trigger == IRQT_FALLING)
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else if (trigger & __IRQT_FALEDGE)
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l &= ~(1 << gpio);
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else
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goto bad;
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@ -491,7 +492,9 @@ static int gpio_irq_type(unsigned irq, unsigned type)
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if (check_gpio(gpio) < 0)
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return -EINVAL;
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if (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL|IRQT_PROBE))
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if (type & IRQT_PROBE)
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return -EINVAL;
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if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
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return -EINVAL;
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bank = get_gpio_bank(gpio);
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@ -755,13 +758,32 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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if (bank->method == METHOD_GPIO_24XX)
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isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
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#endif
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while(1) {
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isr = __raw_readl(isr_reg);
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_enable_gpio_irqbank(bank, isr, 0);
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_clear_gpio_irqbank(bank, isr);
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_enable_gpio_irqbank(bank, isr, 1);
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desc->chip->unmask(irq);
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u32 isr_saved, level_mask = 0;
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isr_saved = isr = __raw_readl(isr_reg);
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if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
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isr &= 0x0000ffff;
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if (cpu_is_omap24xx())
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level_mask =
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__raw_readl(bank->base +
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OMAP24XX_GPIO_LEVELDETECT0) |
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__raw_readl(bank->base +
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OMAP24XX_GPIO_LEVELDETECT1);
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/* clear edge sensitive interrupts before handler(s) are
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called so that we don't miss any interrupt occurred while
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executing them */
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_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
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_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
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_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
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/* if there is only edge sensitive GPIO pin interrupts
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configured, we could unmask GPIO bank interrupt immediately */
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if (!level_mask)
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desc->chip->unmask(irq);
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if (!isr)
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break;
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@ -774,6 +796,20 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
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d = irq_desc + gpio_irq;
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desc_handle_irq(gpio_irq, d, regs);
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}
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if (cpu_is_omap24xx()) {
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/* clear level sensitive interrupts after handler(s) */
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_enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
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_clear_gpio_irqbank(bank, isr_saved & level_mask);
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_enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
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}
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/* if bank has any level sensitive GPIO pin interrupt
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configured, we must unmask the bank interrupt only after
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handler(s) are executed in order to avoid spurious bank
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interrupt */
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if (level_mask)
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desc->chip->unmask(irq);
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}
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}
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@ -848,7 +884,7 @@ static int __init _omap_gpio_init(void)
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initialized = 1;
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if (cpu_is_omap1510()) {
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if (cpu_is_omap15xx()) {
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gpio_ick = clk_get(NULL, "arm_gpio_ck");
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if (IS_ERR(gpio_ick))
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printk("Could not get arm_gpio_ck\n");
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@ -869,7 +905,7 @@ static int __init _omap_gpio_init(void)
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}
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap1510()) {
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if (cpu_is_omap15xx()) {
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printk(KERN_INFO "OMAP1510 GPIO hardware\n");
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gpio_bank_count = 2;
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gpio_bank = gpio_bank_1510;
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