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EDAC, MCE: Fix NB error formatting 

Minor formatting fixup since the information which core was associated
with the MCE is not always valid.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov 2010-11-25 15:40:27 +01:00
parent 50adbbd8a8
commit 6d5db46687
1 changed files with 10 additions and 7 deletions
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17
drivers/edac/mce_amd.c
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@ -597,24 +597,27 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
u16 ec = EC(m->status); u16 ec = EC(m->status);
u8 xec = XEC(m->status, 0x1f); u8 xec = XEC(m->status, 0x1f);
u32 nbsh = (u32)(m->status >> 32); u32 nbsh = (u32)(m->status >> 32);
int core = -1;
pr_emerg(HW_ERR "Northbridge Error, node %d: ", node_id); pr_emerg(HW_ERR "Northbridge Error (node %d", node_id);
/* /* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */
* F10h, revD can disable ErrCpu[3:0] so check that first and also the
* value encoding has changed so interpret those differently
*/
if ((boot_cpu_data.x86 == 0x10) && if ((boot_cpu_data.x86 == 0x10) &&
(boot_cpu_data.x86_model > 7)) { (boot_cpu_data.x86_model > 7)) {
if (nbsh & K8_NBSH_ERR_CPU_VAL) if (nbsh & K8_NBSH_ERR_CPU_VAL)
pr_cont(", core: %u", (u8)(nbsh & nb_err_cpumask)); core = nbsh & nb_err_cpumask;
} else { } else {
u8 assoc_cpus = nbsh & nb_err_cpumask; u8 assoc_cpus = nbsh & nb_err_cpumask;
if (assoc_cpus > 0) if (assoc_cpus > 0)
pr_cont(", core: %d", fls(assoc_cpus) - 1); core = fls(assoc_cpus) - 1;
} }
if (core >= 0)
pr_cont(", core %d): ", core);
else
pr_cont("): ");
switch (xec) { switch (xec) {
case 0x2: case 0x2:
pr_cont("Sync error (sync packets on HT link detected).\n"); pr_cont("Sync error (sync packets on HT link detected).\n");