dect
/
linux-2.6
Archived
13
0
Fork 0
Code Releases Activity

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Count timer interrupts correctly.
  [MIPS] SMTC and non-SMTC kernel and modules are incompatible
  [MIPS] EMMA2RH: Disable GEN_RTC, it can't possibly work.
  [MIPS] Remove a duplicated local variable in test_and_clear_bit()
  [MIPS] use compat_siginfo in rt_sigframe_n32
  [MIPS] 20K: Handle WAIT related bugs according to errata information
  [MIPS] AP/SP requires shadow registers, auto enable support.
  [MIPS] Fix pb1500 reg B access
  [MIPS] Alchemy: Fix wrong cast
  [MIPS] remove "support for" from system type entry
  [MIPS] add io_map_base to pci_controller on Cobalt
  [MIPS] __ucmpdi2 arguments are unsigned long long.
This commit is contained in:
Linus Torvalds 2007-06-26 16:50:48 -07:00
parent 2c9dbda360 8e15a0e35f
commit 6cd236e005
13 changed files with 94 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/mips/Kconfig
View File

@ -317,7 +317,7 @@ config PNX8550_JBS
select SYS_SUPPORTS_LITTLE_ENDIAN
config PNX8550_STB810
bool "Support for Philips PNX8550 based STB810 board"
bool "Philips PNX8550 based STB810 board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -392,7 +392,7 @@ config QEMU
can be found at http://www.linux-mips.org/wiki/Qemu.
config MARKEINS
bool "Support for NEC EMMA2RH Mark-eins"
bool "NEC EMMA2RH Mark-eins"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
@ -1392,6 +1392,7 @@ config MIPS_VPE_LOADER
depends on SYS_SUPPORTS_MULTITHREADING
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
help
Includes a loader for loading an elf relocatable object

2
arch/mips/au1000/pb1100/init.c
View File

@ -53,7 +53,7 @@ void __init prom_init(void)
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (int *) fw_arg3;
prom_envp = (char **) fw_arg3;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1100;

2
arch/mips/au1000/pb1500/board_setup.c
View File

@ -125,7 +125,7 @@ void __init board_setup(void)
au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
}
/* Put the clock in BCD mode */
if (readl(0xac00002C) & 0x4) { /* reg B */
if (au_readl(0xac00002C) & 0x4) { /* reg B */
au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
au_sync();
}

1
arch/mips/cobalt/pci.c
View File

@ -35,6 +35,7 @@ static struct pci_controller cobalt_pci_controller = {
.mem_resource = &cobalt_mem_resource,
.io_resource = &cobalt_io_resource,
.io_offset = 0 - GT_DEF_PCI0_IO_BASE,
.io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
};
static int __init cobalt_pci_init(void)

3
arch/mips/configs/emma2rh_defconfig
View File

@ -951,8 +951,7 @@ CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
CONFIG_RTC=m
CONFIG_GEN_RTC=m
CONFIG_GEN_RTC_X=y
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set

12
arch/mips/kernel/cpu-probe.c
View File

@ -137,7 +137,6 @@ static inline void check_wait(void)
case CPU_4KEC:
case CPU_4KSC:
case CPU_5KC:
/* case CPU_20KC:*/
case CPU_24K:
case CPU_25KF:
case CPU_34K:
@ -156,6 +155,17 @@ static inline void check_wait(void)
if (allow_au1k_wait)
cpu_wait = au1k_wait;
break;
case CPU_20KC:
/*
* WAIT on Rev1.0 has E1, E2, E3 and E16.
* WAIT on Rev2.0 and Rev3.0 has E16.
* Rev3.1 WAIT is nop, why bother
*/
if ((c->processor_id & 0xff) <= 0x64)
break;
cpu_wait = r4k_wait;
break;
case CPU_RM9000:
if ((c->processor_id & 0x00ff) >= 0x40)
cpu_wait = r4k_wait;

62
arch/mips/kernel/signal32.c
View File

@ -36,68 +36,6 @@
#include "signal-common.h"
#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
typedef struct compat_siginfo {
int si_signo;
int si_code;
int si_errno;
union {
int _pad[SI_PAD_SIZE32];
/* kill() */
struct {
compat_pid_t _pid; /* sender's pid */
compat_uid_t _uid; /* sender's uid */
} _kill;
/* SIGCHLD */
struct {
compat_pid_t _pid; /* which child */
compat_uid_t _uid; /* sender's uid */
int _status; /* exit code */
compat_clock_t _utime;
compat_clock_t _stime;
} _sigchld;
/* IRIX SIGCHLD */
struct {
compat_pid_t _pid; /* which child */
compat_clock_t _utime;
int _status; /* exit code */
compat_clock_t _stime;
} _irix_sigchld;
/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
struct {
s32 _addr; /* faulting insn/memory ref. */
} _sigfault;
/* SIGPOLL, SIGXFSZ (To do ...) */
struct {
int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* POSIX.1b timers */
struct {
timer_t _tid; /* timer id */
int _overrun; /* overrun count */
compat_sigval_t _sigval;/* same as below */
int _sys_private; /* not to be passed to user */
} _timer;
/* POSIX.1b signals */
struct {
compat_pid_t _pid; /* sender's pid */
compat_uid_t _uid; /* sender's uid */
compat_sigval_t _sigval;
} _rt;
} _sifields;
} compat_siginfo_t;
/*
* Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
*/

6
arch/mips/kernel/signal_n32.c
View File

@ -72,7 +72,7 @@ struct ucontextn32 {
struct rt_sigframe_n32 {
u32 rs_ass[4]; /* argument save space for o32 */
u32 rs_code[2]; /* signal trampoline */
struct siginfo rs_info;
struct compat_siginfo rs_info;
struct ucontextn32 rs_uc;
};
@ -81,7 +81,7 @@ struct rt_sigframe_n32 {
struct rt_sigframe_n32 {
u32 rs_ass[4]; /* argument save space for o32 */
u32 rs_pad[2];
struct siginfo rs_info;
struct compat_siginfo rs_info;
struct ucontextn32 rs_uc;
u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */
};
@ -187,7 +187,7 @@ static int setup_rt_frame_n32(struct k_sigaction * ka,
install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn);
/* Create siginfo. */
err |= copy_siginfo_to_user(&frame->rs_info, info);
err |= copy_siginfo_to_user32(&frame->rs_info, info);
/* Create the ucontext. */
err |= __put_user(0, &frame->rs_uc.uc_flags);

2
arch/mips/kernel/smtc.c
View File

@ -822,7 +822,7 @@ void ipi_decode(struct smtc_ipi *pipi)
switch (type_copy) {
case SMTC_CLOCK_TICK:
irq_enter();
kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_perfcount_irq]++;
kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++;
/* Invoke Clock "Interrupt" */
ipi_timer_latch[dest_copy] = 0;
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG

2
arch/mips/lib/ucmpdi2.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h"
word_type __ucmpdi2 (unsigned long a, unsigned long b)
word_type __ucmpdi2 (unsigned long long a, unsigned long long b)
{
const DWunion au = {.ll = a};
const DWunion bu = {.ll = b};

2
include/asm-mips/bitops.h
View File

@ -310,7 +310,7 @@ static inline int test_and_clear_bit(unsigned long nr,
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
unsigned long temp;
__asm__ __volatile__(
" .set mips3 \n"

62
include/asm-mips/compat-signal.h
View File

@ -10,6 +10,68 @@
#include <asm/uaccess.h>
#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
typedef struct compat_siginfo {
int si_signo;
int si_code;
int si_errno;
union {
int _pad[SI_PAD_SIZE32];
/* kill() */
struct {
compat_pid_t _pid; /* sender's pid */
compat_uid_t _uid; /* sender's uid */
} _kill;
/* SIGCHLD */
struct {
compat_pid_t _pid; /* which child */
compat_uid_t _uid; /* sender's uid */
int _status; /* exit code */
compat_clock_t _utime;
compat_clock_t _stime;
} _sigchld;
/* IRIX SIGCHLD */
struct {
compat_pid_t _pid; /* which child */
compat_clock_t _utime;
int _status; /* exit code */
compat_clock_t _stime;
} _irix_sigchld;
/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
struct {
s32 _addr; /* faulting insn/memory ref. */
} _sigfault;
/* SIGPOLL, SIGXFSZ (To do ...) */
struct {
int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* POSIX.1b timers */
struct {
timer_t _tid; /* timer id */
int _overrun; /* overrun count */
compat_sigval_t _sigval;/* same as below */
int _sys_private; /* not to be passed to user */
} _timer;
/* POSIX.1b signals */
struct {
compat_pid_t _pid; /* sender's pid */
compat_uid_t _uid; /* sender's uid */
compat_sigval_t _sigval;
} _rt;
} _sifields;
} compat_siginfo_t;
static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
const sigset_t *s)
{

9
include/asm-mips/module.h
View File

@ -122,6 +122,13 @@ search_module_dbetables(unsigned long addr)
#define MODULE_KERNEL_TYPE "64BIT "
#endif
#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
#ifdef CONFIG_MIPS_MT_SMTC
#define MODULE_KERNEL_SMTC "MT_SMTC "
#else
#define MODULE_KERNEL_SMTC ""
#endif
#define MODULE_ARCH_VERMAGIC \
MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
#endif /* _ASM_MODULE_H */