From 6c98274cba3b68e6d87ddb3b0be2bec449106181 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Mon, 1 Oct 2012 14:46:11 -0700 Subject: [PATCH] staging/olpc_dcon: drop pin frobbing code for xo1.5 This code looks in the PCI config space for pin addresses and sets up some stuff. However, Openfirmware has already done this for us, so there's no need to ever do it in Linux. According to Mitch Bradley, this OFW has been doing this for us since at least B3 builds (pre-mass production). Signed-off-by: Andres Salomon Signed-off-by: Greg Kroah-Hartman --- drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c | 30 -------------------- 1 file changed, 30 deletions(-) diff --git a/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c b/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c index 352dd3db013..6a4d379c16a 100644 --- a/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c +++ b/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c @@ -10,7 +10,6 @@ #include #include -#include #include #include @@ -62,33 +61,6 @@ static int dcon_was_irq(void) static int dcon_init_xo_1_5(struct dcon_priv *dcon) { unsigned int irq; - u_int8_t tmp; - struct pci_dev *pdev; - - pdev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855, NULL); - if (!pdev) { - pr_err("cannot find VX855 PCI ID\n"); - return 1; - } - - pci_read_config_byte(pdev, 0x95, &tmp); - pci_write_config_byte(pdev, 0x95, tmp|0x0c); - - /* Set GPIO8 to GPIO mode, not SSPICLK */ - pci_read_config_byte(pdev, 0xe3, &tmp); - pci_write_config_byte(pdev, 0xe3, tmp | 0x04); - - /* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */ - pci_read_config_byte(pdev, 0xe4, &tmp); - pci_write_config_byte(pdev, 0xe4, tmp|0x08); - - /* clear PMU_RxE1[6] to select SCI on GPIO12 */ - /* clear PMU_RxE0[6] to choose falling edge */ - pci_read_config_byte(pdev, 0xe1, &tmp); - pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12); - pci_read_config_byte(pdev, 0xe0, &tmp); - pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12); dcon_clear_irq(); @@ -101,8 +73,6 @@ static int dcon_init_xo_1_5(struct dcon_priv *dcon) DCON_SOURCE_CPU : DCON_SOURCE_DCON; dcon->pending_src = dcon->curr_src; - pci_dev_put(pdev); - /* we're sharing the IRQ with ACPI */ irq = acpi_gbl_FADT.sci_interrupt; if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {