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Blackfin arch: Fix bug - Kernel does not boot if re-program clocks 

Don't write conflicting data to EBIU_SDBCTL after the SDRAM is
configured. This can cause data corruption, since we might change SDRAM
row and column addressing modes.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich 2008-07-14 16:51:57 +08:00 committed by Bryan Wu
parent 260d5d3517
commit 68e2fc78e5
10 changed files with 12 additions and 158 deletions
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14
arch/blackfin/Kconfig
View File

@ -315,20 +315,6 @@ config MEM_SIZE
depends on BFIN_KERNEL_CLOCK
default 64
config MEM_ADD_WIDTH
int "Memory Address Width"
depends on BFIN_KERNEL_CLOCK
depends on (!BF54x)
range 8 11
default 9 if BFIN533_EZKIT
default 9 if BFIN561_EZKIT
default 9 if H8606_HVSISTEMAS
default 10 if BFIN527_EZKIT
default 10 if BFIN537_STAMP
default 11 if BFIN533_STAMP
default 10 if PNAV10
default 10 if BFIN532_IP0X
config PLL_BYPASS
bool "Bypass PLL"
depends on BFIN_KERNEL_CLOCK

12
arch/blackfin/mach-bf527/head.S
View File

@ -32,7 +32,7 @@
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
@ -185,7 +185,7 @@ ENTRY(__start)
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
@ -318,7 +318,7 @@ ENDPROC(_real_start)
__FINIT
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
/* Enable PHY CLK buffer output */
@ -398,12 +398,6 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
p0.l = LO(EBIU_SDBCTL);
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];

12
arch/blackfin/mach-bf533/head.S
View File

@ -31,7 +31,7 @@
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
@ -186,7 +186,7 @@ ENTRY(__start)
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
@ -319,7 +319,7 @@ ENDPROC(_real_start)
__FINIT
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
@ -390,12 +390,6 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
p0.l = LO(EBIU_SDBCTL);
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];

12
arch/blackfin/mach-bf537/head.S
View File

@ -32,7 +32,7 @@
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
@ -217,7 +217,7 @@ ENTRY(__start)
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
@ -350,7 +350,7 @@ ENDPROC(_real_start)
__FINIT
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
/* Enable PHY CLK buffer output */
@ -430,12 +430,6 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
p0.l = LO(EBIU_SDBCTL);
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];

6
arch/blackfin/mach-bf548/head.S
View File

@ -31,7 +31,7 @@
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
@ -130,7 +130,7 @@ ENTRY(__start)
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
/* Code for initializing Async memory banks */
@ -288,7 +288,7 @@ ENDPROC(_real_start)
__FINIT
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
/* Enable PHY CLK buffer output */

6
arch/blackfin/mach-bf561/head.S
View File

@ -377,12 +377,6 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
p0.l = LO(EBIU_SDBCTL);
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];

27
include/asm-blackfin/mach-bf527/mem_init.h
View File

@ -146,33 +146,6 @@
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_SIZE == 128)
#define SDRAM_SIZE EBSZ_128
#endif
#if (CONFIG_MEM_SIZE == 64)
#define SDRAM_SIZE EBSZ_64
#endif
#if (CONFIG_MEM_SIZE == 32)
#define SDRAM_SIZE EBSZ_32
#endif
#if (CONFIG_MEM_SIZE == 16)
#define SDRAM_SIZE EBSZ_16
#endif
#if (CONFIG_MEM_ADD_WIDTH == 11)
#define SDRAM_WIDTH EBCAW_11
#endif
#if (CONFIG_MEM_ADD_WIDTH == 10)
#define SDRAM_WIDTH EBCAW_10
#endif
#if (CONFIG_MEM_ADD_WIDTH == 9)
#define SDRAM_WIDTH EBCAW_9
#endif
#if (CONFIG_MEM_ADD_WIDTH == 8)
#define SDRAM_WIDTH EBCAW_8
#endif
#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)

27
include/asm-blackfin/mach-bf533/mem_init.h
View File

@ -133,33 +133,6 @@
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_SIZE == 128)
#define SDRAM_SIZE EBSZ_128
#endif
#if (CONFIG_MEM_SIZE == 64)
#define SDRAM_SIZE EBSZ_64
#endif
#if (CONFIG_MEM_SIZE == 32)
#define SDRAM_SIZE EBSZ_32
#endif
#if (CONFIG_MEM_SIZE == 16)
#define SDRAM_SIZE EBSZ_16
#endif
#if (CONFIG_MEM_ADD_WIDTH == 11)
#define SDRAM_WIDTH EBCAW_11
#endif
#if (CONFIG_MEM_ADD_WIDTH == 10)
#define SDRAM_WIDTH EBCAW_10
#endif
#if (CONFIG_MEM_ADD_WIDTH == 9)
#define SDRAM_WIDTH EBCAW_9
#endif
#if (CONFIG_MEM_ADD_WIDTH == 8)
#define SDRAM_WIDTH EBCAW_8
#endif
#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)

27
include/asm-blackfin/mach-bf537/mem_init.h
View File

@ -139,33 +139,6 @@
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_SIZE == 128)
#define SDRAM_SIZE EBSZ_128
#endif
#if (CONFIG_MEM_SIZE == 64)
#define SDRAM_SIZE EBSZ_64
#endif
#if (CONFIG_MEM_SIZE == 32)
#define SDRAM_SIZE EBSZ_32
#endif
#if (CONFIG_MEM_SIZE == 16)
#define SDRAM_SIZE EBSZ_16
#endif
#if (CONFIG_MEM_ADD_WIDTH == 11)
#define SDRAM_WIDTH EBCAW_11
#endif
#if (CONFIG_MEM_ADD_WIDTH == 10)
#define SDRAM_WIDTH EBCAW_10
#endif
#if (CONFIG_MEM_ADD_WIDTH == 9)
#define SDRAM_WIDTH EBCAW_9
#endif
#if (CONFIG_MEM_ADD_WIDTH == 8)
#define SDRAM_WIDTH EBCAW_8
#endif
#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)

27
include/asm-blackfin/mach-bf561/mem_init.h
View File

@ -131,33 +131,6 @@
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_SIZE == 128)
#define SDRAM_SIZE EB0_SZ_128
#endif
#if (CONFIG_MEM_SIZE == 64)
#define SDRAM_SIZE EB0_SZ_64
#endif
#if ( CONFIG_MEM_SIZE == 32)
#define SDRAM_SIZE EB0_SZ_32
#endif
#if (CONFIG_MEM_SIZE == 16)
#define SDRAM_SIZE EB0_SZ_16
#endif
#if (CONFIG_MEM_ADD_WIDTH == 11)
#define SDRAM_WIDTH EB0_CAW_11
#endif
#if (CONFIG_MEM_ADD_WIDTH == 10)
#define SDRAM_WIDTH EB0_CAW_10
#endif
#if (CONFIG_MEM_ADD_WIDTH == 9)
#define SDRAM_WIDTH EB0_CAW_9
#endif
#if (CONFIG_MEM_ADD_WIDTH == 8)
#define SDRAM_WIDTH EB0_CAW_8
#endif
#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)