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ARM: spear: convert to MULTI_IRQ_HANDLER 

Now that there is a generic IRQ handler for multiple VIC devices use it
for spear to help building multi platform kernels.

Acked-by: Viresh Kumar <viresh.kumar@st.com>
Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
This commit is contained in:
Jamie Iles 2011-09-27 20:35:14 +01:00 committed by Marc Zyngier
parent 774b51f8f8
commit 66266f4ab8
7 changed files with 9 additions and 63 deletions
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1
arch/arm/Kconfig
View File

@ -955,6 +955,7 @@ config PLAT_SPEAR
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select MULTI_IRQ_HANDLER
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).

27
arch/arm/mach-spear3xx/include/mach/entry-macro.S
View File

@ -11,35 +11,8 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <mach/hardware.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
teq \irqstat, #0
beq 1001f @ this will set/reset
@ zero register
/*
* Following code will find bit position of least significang
* bit set in irqstat, using following equation
* least significant bit set in n = (n & ~(n-1))
*/
sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
mvn \tmp, \tmp @ tmp = ~tmp
and \irqstat, \irqstat, \tmp @ irqstat &= tmp
/* Now, irqstat is = bit no. of 1st bit set in vic irq status */
clz \tmp, \irqstat @ tmp = leading zeros
rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1
1001: /* EQ will be set if no irqs pending */
.endm

2
arch/arm/mach-spear3xx/spear300_evb.c
View File

@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
@ -67,6 +68,7 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
.atag_offset = 0x100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &spear3xx_timer,
.init_machine = spear300_evb_init,
MACHINE_END

2
arch/arm/mach-spear3xx/spear310_evb.c
View File

@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
@ -73,6 +74,7 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
.atag_offset = 0x100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &spear3xx_timer,
.init_machine = spear310_evb_init,
MACHINE_END

2
arch/arm/mach-spear3xx/spear320_evb.c
View File

@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
@ -71,6 +72,7 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
.atag_offset = 0x100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &spear3xx_timer,
.init_machine = spear320_evb_init,
MACHINE_END

36
arch/arm/mach-spear6xx/include/mach/entry-macro.S
View File

@ -11,44 +11,8 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <mach/hardware.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
mov \irqnr, #0
teq \irqstat, #0
bne 1001f
ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
teq \irqstat, #0
beq 1002f @ this will set/reset
@ zero register
mov \irqnr, #32
1001:
/*
* Following code will find bit position of least significang
* bit set in irqstat, using following equation
* least significant bit set in n = (n & ~(n-1))
*/
sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
mvn \tmp, \tmp @ tmp = ~tmp
and \irqstat, \irqstat, \tmp @ irqstat &= tmp
/* Now, irqstat is = bit no. of 1st bit set in vic irq status */
clz \tmp, \irqstat @ tmp = leading zeros
rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1
add \irqnr, \irqnr, \tmp
1002: /* EQ will be set if no irqs pending */
.endm

2
arch/arm/mach-spear6xx/spear600_evb.c
View File

@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
@ -46,6 +47,7 @@ MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
.atag_offset = 0x100,
.map_io = spear6xx_map_io,
.init_irq = spear6xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &spear6xx_timer,
.init_machine = spear600_evb_init,
MACHINE_END