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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (187 commits)
  sh: remove dead LED code for migo-r and ms7724se
  sh: ecovec build fix for CONFIG_I2C=n
  sh: ecovec r-standby support
  sh: ms7724se r-standby support
  sh: SH-Mobile R-standby register save/restore
  clocksource: Fix up a registration/IRQ race in the sh drivers.
  sh: ms7724: modify scan_timing for KEYSC
  sh: ms7724: Add sh_sir support
  sh: mach-ecovec24: Add sh_sir support
  sh: wire up SET/GET_UNALIGN_CTL.
  sh: allow alignment fault mode to be configured at kernel boot.
  sh: sh7724: Update FSI/SPU2 clock
  sh: always enable sh7724 vpu_clk and set to 166MHz on Ecovec
  sh: add sh7724 kick callback to clk_div4_table
  sh: introduce struct clk_div4_table
  sh: clock-cpg div4 set_rate() shift fix
  sh: Turn on speculative return for SH7785 and SH7786
  sh: Merge legacy and dynamic PMB modes.
  sh: Use uncached I/O helpers in PMB setup.
  sh: Provide uncached I/O helpers.
  ...
This commit is contained in:
Linus Torvalds 2010-02-26 16:54:27 -08:00
parent 37d4008484 b5f5fe80fa
commit 64d497f553
288 changed files with 9167 additions and 4463 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
arch/sh/Kconfig
View File

@ -13,7 +13,6 @@ config SUPERH
select HAVE_LMB
select HAVE_OPROFILE
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IOREMAP_PROT if MMU
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select HAVE_DMA_ATTRS
@ -22,6 +21,7 @@ config SUPERH
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select HAVE_SYSCALL_TRACEPOINTS
select RTC_LIB
select GENERIC_ATOMIC64
@ -35,6 +35,7 @@ config SUPERH32
def_bool ARCH = "sh"
select HAVE_KPROBES
select HAVE_KRETPROBES
select HAVE_IOREMAP_PROT if MMU && !X2TLB
select HAVE_FUNCTION_TRACER
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_DYNAMIC_FTRACE
@ -42,6 +43,8 @@ config SUPERH32
select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_ARCH_KGDB
select HAVE_HW_BREAKPOINT
select PERF_EVENTS if HAVE_HW_BREAKPOINT
select ARCH_HIBERNATION_POSSIBLE if MMU
config SUPERH64
@ -78,12 +81,13 @@ config GENERIC_HARDIRQS
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_IRQ_PROBE
def_bool y
config IRQ_PER_CPU
def_bool y
config SPARSE_IRQ
def_bool y
depends on SUPERH32
config GENERIC_GPIO
def_bool n
@ -548,8 +552,7 @@ config SH_PCLK_FREQ
CPU_SUBTYPE_SH7203 || \
CPU_SUBTYPE_SH7206 || \
CPU_SUBTYPE_SH7263 || \
CPU_SUBTYPE_MXG || \
CPU_SUBTYPE_SH7786
CPU_SUBTYPE_MXG
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
default "66000000" if CPU_SUBTYPE_SH4_202
default "50000000"
@ -563,7 +566,8 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SUBTYPE_SH7786
config SH_CLK_MD
int "CPU Mode Pin Setting"
@ -725,18 +729,6 @@ config GUSA_RB
LLSC, this should be more efficient than the other alternative of
disabling interrupts around the atomic sequence.
config SPARSE_IRQ
bool "Support sparse irq numbering"
depends on EXPERIMENTAL
help
This enables support for sparse irqs. This is useful in general
as most CPUs have a fairly sparse array of IRQ vectors, which
the irq_desc then maps directly on to. Systems with a high
number of off-chip IRQs will want to treat this as
experimental until they have been independently verified.
If you don't know what to do here, say N.
endmenu
menu "Boot options"
@ -822,11 +814,15 @@ config MAPLE
config PCI
bool "PCI support"
depends on SYS_SUPPORTS_PCI
select PCI_DOMAINS
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
your box. If you have PCI, say Y, otherwise N.
config PCI_DOMAINS
bool
source "drivers/pci/pcie/Kconfig"
source "drivers/pci/Kconfig"

3
arch/sh/Kconfig.cpu
View File

@ -68,7 +68,8 @@ config SH_STORE_QUEUES
config SPECULATIVE_EXECUTION
bool "Speculative subroutine return"
depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
depends on EXPERIMENTAL
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
help
This enables support for a speculative instruction fetch for
subroutine return. There are various pitfalls associated with

10
arch/sh/Makefile
View File

@ -83,6 +83,7 @@ defaultimage-$(CONFIG_SH_AP325RXA) := uImage
defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE) := uImage
defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
defaultimage-$(CONFIG_SH_SDK7786) := vmlinux.bin
# Set some sensible Kbuild defaults
KBUILD_IMAGE := $(defaultimage-y)
@ -143,11 +144,11 @@ machdir-$(CONFIG_SH_AP325RXA) += mach-ap325rxa
machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09
machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24
machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780
machdir-$(CONFIG_SH_SDK7786) += mach-sdk7786
machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto
machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp
machdir-$(CONFIG_SH_SH4202_MICRODEV) += mach-microdev
machdir-$(CONFIG_SH_LANDISK) += mach-landisk
machdir-$(CONFIG_SH_TITAN) += mach-titan
machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2
machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
machdir-$(CONFIG_SH_RSK) += mach-rsk
@ -203,8 +204,9 @@ endif
libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec uImage.bin \
zImage vmlinux.srec romImage
BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.lzo \
uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
romImage
PHONY += $(BOOT_TARGETS)
all: $(KBUILD_IMAGE)
@ -225,10 +227,12 @@ define archhelp
@echo ' zImage - Compressed kernel image'
@echo ' romImage - Compressed ROM image, if supported'
@echo ' vmlinux.srec - Create an ELF S-record'
@echo ' vmlinux.bin - Create an uncompressed binary image'
@echo '* uImage - Alias to bootable U-Boot image'
@echo ' uImage.srec - Create an S-record for U-Boot'
@echo ' uImage.bin - Kernel-only image for U-Boot (bin)'
@echo '* uImage.gz - Kernel-only image for U-Boot (gzip)'
@echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)'
@echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)'
@echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)'
endef

8
arch/sh/boards/Kconfig
View File

@ -150,6 +150,14 @@ config SH_SDK7780
Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
evaluation board.
config SH_SDK7786
bool "SDK7786"
depends on CPU_SUBTYPE_SH7786
select SYS_SUPPORTS_PCI
help
Select SDK7786 if configuring for a Renesas Technology Europe
SH7786-65nm board.
config SH_HIGHLANDER
bool "Highlander"
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785

1
arch/sh/boards/Makefile
View File

@ -8,3 +8,4 @@ obj-$(CONFIG_SH_SHMIN) += board-shmin.o
obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
obj-$(CONFIG_SH_ESPT) += board-espt.o
obj-$(CONFIG_SH_POLARIS) += board-polaris.o
obj-$(CONFIG_SH_TITAN) += board-titan.o

74
arch/sh/boards/board-magicpanelr2.c
View File

@ -23,7 +23,7 @@
#include <asm/heartbeat.h>
#include <cpu/sh7720.h>
#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL)
#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
/* Prefer cmdline over RedBoot */
static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
@ -60,33 +60,33 @@ static void __init setup_chip_select(void)
{
/* CS2: LAN (0x08000000 - 0x0bffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x36db0400, CS2BCR);
__raw_writel(0x36db0400, CS2BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x000003c0, CS2WCR);
__raw_writel(0x000003c0, CS2WCR);
/* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS4BCR);
__raw_writel(0x00000200, CS4BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS4WCR);
__raw_writel(0x00100981, CS4WCR);
/* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5ABCR);
__raw_writel(0x00000200, CS5ABCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5AWCR);
__raw_writel(0x00100981, CS5AWCR);
/* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5BBCR);
__raw_writel(0x00000200, CS5BBCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5BWCR);
__raw_writel(0x00100981, CS5BWCR);
/* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS6ABCR);
__raw_writel(0x00000200, CS6ABCR);
/* (SW:1.5 WR:3 HW:1.5), no ext. wait */
ctrl_outl(0x001009C1, CS6AWCR);
__raw_writel(0x001009C1, CS6AWCR);
}
static void __init setup_port_multiplexing(void)
@ -94,71 +94,71 @@ static void __init setup_port_multiplexing(void)
/* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
* A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
*/
ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
/* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
* B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
*/
ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
/* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
* C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
*/
ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
__raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
/* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
* D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
*/
ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
/* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
* E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
*/
ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
__raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
/* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
* F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
*/
ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
__raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
/* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
* G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
*/
ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
__raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
/* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
* H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
*/
ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
__raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
/* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
* J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
*/
ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
__raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
/* K7 (x); K6 (x); K5 (x); K4 (x);
* K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
*/
ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
__raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
/* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
* L3 TCK; L2 (x); L1 (x); L0 (x);
*/
ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
__raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
/* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
* M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
* M1 CS5B(CAN3_CS); M0 GPI+(nc);
*/
ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
__raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
/* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
* LAN_RESET=off, BUZZER=off, LCD_BL=off
*/
#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
ctrl_outb(0x30, PORT_PMDR);
__raw_writeb(0x30, PORT_PMDR);
#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
ctrl_outb(0xF0, PORT_PMDR);
__raw_writeb(0xF0, PORT_PMDR);
#else
#error Unknown revision of PLATFORM_MP_R2
#endif
@ -167,8 +167,8 @@ static void __init setup_port_multiplexing(void)
* P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
* P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
*/
ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
ctrl_outb(0x10, PORT_PPDR);
__raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
__raw_writeb(0x10, PORT_PPDR);
/* R7 A25; R6 A24; R5 A23; R4 A22;
* R3 A21; R2 A20; R1 A19; R0 A0;
@ -185,22 +185,22 @@ static void __init setup_port_multiplexing(void)
/* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
* S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
*/
ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
__raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
/* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
* T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
*/
ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
__raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
/* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
* U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
*/
ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
__raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
/* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
* V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
*/
ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
__raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
}
static void __init mpr2_setup(char **cmdline_p)
@ -209,24 +209,24 @@ static void __init mpr2_setup(char **cmdline_p)
* /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
* /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
*/
ctrl_outw(0xAABC, PORT_PSELA);
__raw_writew(0xAABC, PORT_PSELA);
/* set Pin Select Register B:
* /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
* LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
*/
ctrl_outw(0x3C00, PORT_PSELB);
__raw_writew(0x3C00, PORT_PSELB);
/* set Pin Select Register C:
* SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
*/
ctrl_outw(0x0000, PORT_PSELC);
__raw_writew(0x0000, PORT_PSELC);
/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
* Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
*/
ctrl_outw(0x0000, PORT_PSELD);
__raw_writew(0x0000, PORT_PSELD);
/* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
ctrl_outw(0x0101, PORT_UTRCTL);
__raw_writew(0x0101, PORT_UTRCTL);
/* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
ctrl_outw(0xA5C0, PORT_UCLKCR_W);
__raw_writew(0xA5C0, PORT_UCLKCR_W);
setup_chip_select();

37
arch/sh/boards/board-polaris.c
View File

@ -59,15 +59,12 @@ static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 8,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PORT_PCDR,
.end = PORT_PCDR,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PORT_PCDR,
.end = PORT_PCDR,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};
static struct platform_device heartbeat_device = {
@ -76,8 +73,8 @@ static struct platform_device heartbeat_device = {
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct platform_device *polaris_devices[] __initdata = {
@ -92,15 +89,15 @@ static int __init polaris_initialise(void)
printk(KERN_INFO "Configuring Polaris external bus\n");
/* Configure area 5 with 2 wait states */
wcr = ctrl_inw(WCR2);
wcr = __raw_readw(WCR2);
wcr &= (~AREA5_WAIT_CTRL);
wcr |= (WAIT_STATES_10 << 10);
ctrl_outw(wcr, WCR2);
__raw_writew(wcr, WCR2);
/* Configure area 5 for 32-bit access */
bcr_mask = ctrl_inw(BCR2);
bcr_mask = __raw_readw(BCR2);
bcr_mask |= 1 << 10;
ctrl_outw(bcr_mask, BCR2);
__raw_writew(bcr_mask, BCR2);
return platform_add_devices(polaris_devices,
ARRAY_SIZE(polaris_devices));
@ -131,13 +128,13 @@ static struct ipr_desc ipr_irq_desc = {
static void __init init_polaris_irq(void)
{
/* Disable all interrupts */
ctrl_outw(0, BCR_ILCRA);
ctrl_outw(0, BCR_ILCRB);
ctrl_outw(0, BCR_ILCRC);
ctrl_outw(0, BCR_ILCRD);
ctrl_outw(0, BCR_ILCRE);
ctrl_outw(0, BCR_ILCRF);
ctrl_outw(0, BCR_ILCRG);
__raw_writew(0, BCR_ILCRA);
__raw_writew(0, BCR_ILCRB);
__raw_writew(0, BCR_ILCRC);
__raw_writew(0, BCR_ILCRD);
__raw_writew(0, BCR_ILCRE);
__raw_writew(0, BCR_ILCRF);
__raw_writew(0, BCR_ILCRG);
register_ipr_controller(&ipr_irq_desc);
}

32
arch/sh/boards/board-sh7785lcr.c
View File

@ -21,6 +21,7 @@
#include <linux/i2c-algo-pca.h>
#include <linux/usb/r8a66597.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <mach/sh7785lcr.h>
@ -32,26 +33,17 @@
* NOTE: This board has 2 physical memory maps.
* Please look at include/asm-sh/sh7785lcr.h or hardware manual.
*/
static struct resource heartbeat_resources[] = {
[0] = {
.start = PLD_LEDCR,
.end = PLD_LEDCR,
.flags = IORESOURCE_MEM,
},
};
static struct heartbeat_data heartbeat_data = {
.regsize = 8,
static struct resource heartbeat_resource = {
.start = PLD_LEDCR,
.end = PLD_LEDCR,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct mtd_partition nor_flash_partitions[] = {
@ -341,8 +333,14 @@ static void __init sh7785lcr_setup(char **cmdline_p)
pm_power_off = sh7785lcr_power_off;
/* sm501 DRAM configuration */
sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
writel(0x000307c2, sm501_reg);
sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
if (!sm501_reg) {
printk(KERN_ERR "%s: ioremap error.\n", __func__);
return;
}
writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
iounmap(sm501_reg);
}
/* Return the board specific boot mode pin configuration */

4
arch/sh/boards/board-shmin.c
View File

@ -17,8 +17,8 @@
static void __init init_shmin_irq(void)
{
ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
__raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
__raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
plat_irq_setup_pins(IRQ_MODE_IRQ);
}

24
arch/sh/boards/mach-titan/setup.c → arch/sh/boards/board-titan.c
View File

@ -19,26 +19,6 @@ static void __init init_titan_irq(void)
}
static struct sh_machine_vector mv_titan __initmv = {
.mv_name = "Titan",
.mv_inb = titan_inb,
.mv_inw = titan_inw,
.mv_inl = titan_inl,
.mv_outb = titan_outb,
.mv_outw = titan_outw,
.mv_outl = titan_outl,
.mv_inb_p = titan_inb_p,
.mv_inw_p = titan_inw,
.mv_inl_p = titan_inl,
.mv_outb_p = titan_outb_p,
.mv_outw_p = titan_outw,
.mv_outl_p = titan_outl,
.mv_insl = titan_insl,
.mv_outsl = titan_outsl,
.mv_ioport_map = titan_ioport_map,
.mv_init_irq = init_titan_irq,
.mv_name = "Titan",
.mv_init_irq = init_titan_irq,
};

46
arch/sh/boards/board-urquell.c
View File

@ -2,7 +2,7 @@
* Renesas Technology Corp. SH7786 Urquell Support.
*
* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Copyright (C) 2009 Paul Mundt
* Copyright (C) 2009, 2010 Paul Mundt
*
* Based on board-sh7785lcr.c
* Copyright (C) 2008 Yoshihiro Shimoda
@ -19,6 +19,7 @@
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <mach/urquell.h>
#include <cpu/sh7786.h>
#include <asm/heartbeat.h>
@ -50,26 +51,17 @@
*/
/* HeartBeat */
static struct resource heartbeat_resources[] = {
[0] = {
.start = BOARDREG(SLEDR),
.end = BOARDREG(SLEDR),
.flags = IORESOURCE_MEM,
},
};
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
static struct resource heartbeat_resource = {
.start = BOARDREG(SLEDR),
.end = BOARDREG(SLEDR),
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* LAN91C111 */
@ -184,6 +176,27 @@ static int urquell_mode_pins(void)
return __raw_readw(UBOARDREG(MDSWMR));
}
static int urquell_clk_init(void)
{
struct clk *clk;
int ret;
/*
* Only handle the EXTAL case, anyone interfacing a crystal
* resonator will need to provide their own input clock.
*/
if (test_mode_pin(MODE_PIN9))
return -EINVAL;
clk = clk_get(NULL, "extal");
if (!clk || IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
return ret;
}
/* Initialize the board */
static void __init urquell_setup(char **cmdline_p)
{
@ -200,4 +213,5 @@ static struct sh_machine_vector mv_urquell __initmv = {
.mv_setup = urquell_setup,
.mv_init_irq = urquell_init_irq,
.mv_mode_pins = urquell_mode_pins,
.mv_clk_init = urquell_clk_init,
};

20
arch/sh/boards/mach-ap325rxa/setup.c
View File

@ -159,21 +159,21 @@ static void ap320_wvga_power_on(void *board_data)
msleep(100);
/* ASD AP-320/325 LCD ON */
ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
/* backlight */
gpio_set_value(GPIO_PTS3, 0);
ctrl_outw(0x100, FPGA_BKLREG);
__raw_writew(0x100, FPGA_BKLREG);
}
static void ap320_wvga_power_off(void *board_data)
{
/* backlight */
ctrl_outw(0, FPGA_BKLREG);
__raw_writew(0, FPGA_BKLREG);
gpio_set_value(GPIO_PTS3, 1);
/* ASD AP-320/325 LCD OFF */
ctrl_outw(0, FPGA_LCDREG);
__raw_writew(0, FPGA_LCDREG);
}
static struct sh_mobile_lcdc_info lcdc_info = {
@ -420,7 +420,7 @@ static struct resource sdhi0_cn3_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 101,
.start = 100,
.flags = IORESOURCE_IRQ,
},
};
@ -443,7 +443,7 @@ static struct resource sdhi1_cn7_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 24,
.start = 23,
.flags = IORESOURCE_IRQ,
},
};
@ -595,7 +595,7 @@ static int __init ap325rxa_devices_setup(void)
gpio_request(GPIO_PTZ4, NULL);
gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
/* FLCTL */
gpio_request(GPIO_FN_FCE, NULL);
@ -613,9 +613,9 @@ static int __init ap325rxa_devices_setup(void)
gpio_request(GPIO_FN_FWE, NULL);
gpio_request(GPIO_FN_FRB, NULL);
ctrl_outw(0, PORT_HIZCRC);
ctrl_outw(0xFFFF, PORT_DRVCRA);
ctrl_outw(0xFFFF, PORT_DRVCRB);
__raw_writew(0, PORT_HIZCRC);
__raw_writew(0xFFFF, PORT_DRVCRA);
__raw_writew(0xFFFF, PORT_DRVCRB);
platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);

16
arch/sh/boards/mach-cayman/irq.c
View File

@ -66,9 +66,9 @@ static void enable_cayman_irq(unsigned int irq)
reg = EPLD_MASK_BASE + ((irq / 8) << 2);
bit = 1<<(irq % 8);
local_irq_save(flags);
mask = ctrl_inl(reg);
mask = __raw_readl(reg);
mask |= bit;
ctrl_outl(mask, reg);
__raw_writel(mask, reg);
local_irq_restore(flags);
}
@ -83,9 +83,9 @@ void disable_cayman_irq(unsigned int irq)
reg = EPLD_MASK_BASE + ((irq / 8) << 2);
bit = 1<<(irq % 8);
local_irq_save(flags);
mask = ctrl_inl(reg);
mask = __raw_readl(reg);
mask &= ~bit;
ctrl_outl(mask, reg);
__raw_writel(mask, reg);
local_irq_restore(flags);
}
@ -109,8 +109,8 @@ int cayman_irq_demux(int evt)
unsigned long status;
int i;
status = ctrl_inl(EPLD_STATUS_BASE) &
ctrl_inl(EPLD_MASK_BASE) & 0xff;
status = __raw_readl(EPLD_STATUS_BASE) &
__raw_readl(EPLD_MASK_BASE) & 0xff;
if (status == 0) {
irq = -1;
} else {
@ -126,8 +126,8 @@ int cayman_irq_demux(int evt)
unsigned long status;
int i;
status = ctrl_inl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
ctrl_inl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
__raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
if (status == 0) {
irq = -1;
} else {

27
arch/sh/boards/mach-dreamcast/irq.c
View File

@ -135,3 +135,30 @@ int systemasic_irq_demux(int irq)
/* Not reached */
return irq;
}
void systemasic_irq_init(void)
{
int i, nid = cpu_to_node(boot_cpu_data);
/* Assign all virtual IRQs to the System ASIC int. handler */
for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
unsigned int irq;
irq = create_irq_nr(i, nid);
if (unlikely(irq == 0)) {
pr_err("%s: failed hooking irq %d for systemasic\n",
__func__, i);
return;
}
if (unlikely(irq != i)) {
pr_err("%s: got irq %d but wanted %d, bailing.\n",
__func__, irq, i);
destroy_irq(irq);
return;
}
set_irq_chip_and_handler(i, &systemasic_int,
handle_level_irq);
}
}

20
arch/sh/boards/mach-dreamcast/rtc.c
View File

@ -35,11 +35,11 @@ static void aica_rtc_gettimeofday(struct timespec *ts)
unsigned long val1, val2;
do {
val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
} while (val1 != val2);
ts->tv_sec = val1 - TWENTY_YEARS;
@ -60,14 +60,14 @@ static int aica_rtc_settimeofday(const time_t secs)
unsigned long adj = secs + TWENTY_YEARS;
do {
ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L);
__raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
__raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
} while (val1 != val2);
return 0;

18
arch/sh/boards/mach-dreamcast/setup.c
View File

@ -28,25 +28,8 @@
#include <asm/machvec.h>
#include <mach/sysasic.h>
extern struct irq_chip systemasic_int;
extern void aica_time_init(void);
extern int systemasic_irq_demux(int);
static void __init dreamcast_setup(char **cmdline_p)
{
int i;
/* Mask all hardware events */
/* XXX */
/* Acknowledge any previous events */
/* XXX */
/* Assign all virtual IRQs to the System ASIC int. handler */
for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
set_irq_chip_and_handler(i, &systemasic_int,
handle_level_irq);
board_time_init = aica_time_init;
}
@ -54,4 +37,5 @@ static struct sh_machine_vector mv_dreamcast __initmv = {
.mv_name = "Sega Dreamcast",
.mv_setup = dreamcast_setup,
.mv_irq_demux = systemasic_irq_demux,
.mv_init_irq = systemasic_irq_init,
};

59
arch/sh/boards/mach-ecovec24/sdram.S
View File

@ -37,6 +37,10 @@ ENTRY(ecovec24_sdram_enter_end)
.balign 4
ENTRY(ecovec24_sdram_leave_start)
mov.l @(SH_SLEEP_MODE, r5), r0
tst #SUSP_SH_RSTANDBY, r0
bf resume_rstandby
/* DBSC: put memory in auto-refresh mode */
ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
@ -49,4 +53,59 @@ ENTRY(ecovec24_sdram_leave_start)
rts
nop
resume_rstandby:
/* DBSC: re-initialize and put in auto-refresh */
ED 0xFD000108, 0x00000181 /* DBPDCNT0 */
ED 0xFD000020, 0x015B0002 /* DBCONF */
ED 0xFD000030, 0x03071502 /* DBTR0 */
ED 0xFD000034, 0x02020102 /* DBTR1 */
ED 0xFD000038, 0x01090405 /* DBTR2 */
ED 0xFD00003C, 0x00000002 /* DBTR3 */
ED 0xFD000008, 0x00000005 /* DBKIND */
ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
ED 0xFD000018, 0x00000001 /* DBCKECNT */
mov #100,r0
WAIT_400NS:
dt r0
bf WAIT_400NS
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */
ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */
ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */
ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */
ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */
ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */
mov #100,r0
WAIT_400NS_2:
dt r0
bf WAIT_400NS_2
ED 0xFD000010, 0x00000001 /* DBEN */
ED 0xFD000044, 0x0000050f /* DBRFPDN1 */
ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */
mov.l DUMMY,r0
mov.l @r0, r1 /* force single dummy read */
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000108, 0x00000080 /* DBPDCNT0 */
ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
rts
nop
.balign 4
DUMMY: .long 0xac400000
ENTRY(ecovec24_sdram_leave_end)

87
arch/sh/boards/mach-ecovec24/setup.c
View File

@ -64,18 +64,16 @@
/* Heartbeat */
static unsigned char led_pos[] = { 0, 1, 2, 3 };
static struct heartbeat_data heartbeat_data = {
.regsize = 8,
.nr_bits = 4,
.bit_pos = led_pos,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xA405012C, /* PTG */
.end = 0xA405012E - 1,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = 0xA405012C, /* PTG */
.end = 0xA405012E - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};
static struct platform_device heartbeat_device = {
@ -84,8 +82,8 @@ static struct platform_device heartbeat_device = {
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* MTD */
@ -455,7 +453,7 @@ static struct resource sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 101,
.start = 100,
.flags = IORESOURCE_IRQ,
},
};
@ -491,7 +489,7 @@ static struct resource sdhi1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 24,
.start = 23,
.flags = IORESOURCE_IRQ,
},
};
@ -698,13 +696,13 @@ static struct platform_device camera_devices[] = {
#define FCLKBCR 0xa415000c
static void fsimck_init(struct clk *clk)
{
u32 status = ctrl_inl(clk->enable_reg);
u32 status = __raw_readl(clk->enable_reg);
/* use external clock */
status &= ~0x000000ff;
status |= 0x00000080;
ctrl_outl(status, clk->enable_reg);
__raw_writel(status, clk->enable_reg);
}
static struct clk_ops fsimck_clk_ops = {
@ -753,6 +751,26 @@ static struct platform_device fsi_device = {
},
};
/* IrDA */
static struct resource irda_resources[] = {
[0] = {
.name = "IrDA",
.start = 0xA45D0000,
.end = 0xA45D0049,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device irda_device = {
.name = "sh_sir",
.num_resources = ARRAY_SIZE(irda_resources),
.resource = irda_resources,
};
static struct platform_device *ecovec_devices[] __initdata = {
&heartbeat_device,
&nor_flash_device,
@ -773,8 +791,10 @@ static struct platform_device *ecovec_devices[] __initdata = {
&camera_devices[1],
&camera_devices[2],
&fsi_device,
&irda_device,
};
#ifdef CONFIG_I2C
#define EEPROM_ADDR 0x50
static u8 mac_read(struct i2c_adapter *a, u8 command)
{
@ -817,6 +837,12 @@ static void __init sh_eth_init(struct sh_eth_plat_data *pd)
msleep(10);
}
}
#else
static void __init sh_eth_init(struct sh_eth_plat_data *pd)
{
pr_err("unable to read sh_eth MAC address\n");
}
#endif
#define PORT_HIZA 0xA4050158
#define IODRIVEA 0xA405018A
@ -831,7 +857,8 @@ static int __init arch_setup(void)
struct clk *clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&ecovec24_sdram_enter_start,
&ecovec24_sdram_enter_end,
&ecovec24_sdram_leave_start,
@ -855,7 +882,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTG1, 0);
gpio_direction_output(GPIO_PTG2, 0);
gpio_direction_output(GPIO_PTG3, 0);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
__raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
/* enable SH-Eth */
gpio_request(GPIO_PTA1, NULL);
@ -875,16 +902,16 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_LNKSTA, NULL);
/* enable USB */
ctrl_outw(0x0000, 0xA4D80000);
ctrl_outw(0x0000, 0xA4D90000);
__raw_writew(0x0000, 0xA4D80000);
__raw_writew(0x0000, 0xA4D90000);
gpio_request(GPIO_PTB3, NULL);
gpio_request(GPIO_PTB4, NULL);
gpio_request(GPIO_PTB5, NULL);
gpio_direction_input(GPIO_PTB3);
gpio_direction_output(GPIO_PTB4, 0);
gpio_direction_output(GPIO_PTB5, 0);
ctrl_outw(0x0600, 0xa40501d4);
ctrl_outw(0x0600, 0xa4050192);
__raw_writew(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa4050192);
if (gpio_get_value(GPIO_PTB3)) {
printk(KERN_INFO "USB1 function is selected\n");
@ -925,7 +952,7 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
gpio_request(GPIO_PTE6, NULL);
gpio_request(GPIO_PTU1, NULL);
@ -937,7 +964,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTA2, 0);
/* I/O buffer drive ability is high */
ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
__raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
@ -1069,7 +1096,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTB7, 0);
/* I/O buffer drive ability is high for SDHI1 */
ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
#else
/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
@ -1107,6 +1134,11 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
clk_register(&fsimckb_clk);
@ -1123,6 +1155,17 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_direction_input(GPIO_FN_INTC_IRQ1);
/* set VPU clock to 166 MHz */
clk = clk_get(NULL, "vpu_clk");
clk_set_rate(clk, clk_round_rate(clk, 166000000));
clk_put(clk);
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
gpio_request(GPIO_PTU5, NULL);
gpio_direction_output(GPIO_PTU5, 0);
/* enable I2C device */
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));

2
arch/sh/boards/mach-highlander/irq-r7780mp.c
View File

@ -64,7 +64,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) {
if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) {
printk(KERN_INFO "Using r7780mp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;

2
arch/sh/boards/mach-highlander/irq-r7780rp.c
View File

@ -57,7 +57,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if (ctrl_inw(0xa5000600)) {
if (__raw_readw(0xa5000600)) {
printk(KERN_INFO "Using r7780rp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;

16
arch/sh/boards/mach-highlander/irq-r7785rp.c
View File

@ -66,20 +66,20 @@ static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
return NULL;
printk(KERN_INFO "Using r7785rp interrupt controller.\n");
ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
__raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
/* Setup the FPGA IRL */
ctrl_outw(0x0000, PA_IRLPRA); /* FPGA IRLA */
ctrl_outw(0xe598, PA_IRLPRB); /* FPGA IRLB */
ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */
ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */
ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */
ctrl_outw(0xdcba, PA_IRLPRF); /* FPGA IRLF */
__raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
__raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
__raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
__raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
__raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
__raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
register_intc_controller(&intc_desc);
return irl2irq;

4
arch/sh/boards/mach-highlander/psw.c
View File

@ -24,7 +24,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
unsigned int l, mask;
int ret = 0;
l = ctrl_inw(PA_DBSW);
l = __raw_readw(PA_DBSW);
/* Nothing to do if there's no state change */
if (psw->state) {
@ -45,7 +45,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
out:
/* Clear the switch IRQs */
l |= (0x7 << 12);
ctrl_outw(l, PA_DBSW);
__raw_writew(l, PA_DBSW);
return IRQ_RETVAL(ret);
}

14
arch/sh/boards/mach-highlander/setup.c
View File

@ -311,13 +311,13 @@ device_initcall(r7780rp_devices_setup);
*/
static int ivdr_clk_enable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
__raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
return 0;
}
static void ivdr_clk_disable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
__raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
}
static struct clk_ops ivdr_clk_ops = {
@ -337,7 +337,7 @@ static struct clk *r7780rp_clocks[] = {
static void r7780rp_power_off(void)
{
if (mach_is_r7780mp() || mach_is_r7785rp())
ctrl_outw(0x0001, PA_POFF);
__raw_writew(0x0001, PA_POFF);
}
/*
@ -345,7 +345,7 @@ static void r7780rp_power_off(void)
*/
static void __init highlander_setup(char **cmdline_p)
{
u16 ver = ctrl_inw(PA_VERREG);
u16 ver = __raw_readw(PA_VERREG);
int i;
printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
@ -370,12 +370,12 @@ static void __init highlander_setup(char **cmdline_p)
clk_enable(clk);
}
ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
__raw_writew(0x0000, PA_OBLED); /* Clear LED. */
if (mach_is_r7780rp())
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
__raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
__raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
pm_power_off = r7780rp_power_off;
}

2
arch/sh/boards/mach-hp6xx/hp6xx_apm.c
View File

@ -53,7 +53,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info)
info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
APM_AC_ONLINE : APM_AC_OFFLINE;
pgdr = ctrl_inb(PGDR);
pgdr = __raw_readb(PGDR);
if (pgdr & PGDR_MAIN_BATTERY_OUT) {
info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
info->battery_flag = 0x80;

38
arch/sh/boards/mach-hp6xx/pm.c
View File

@ -53,17 +53,17 @@ static void pm_enter(void)
sh_wdt_write_cnt(0);
/* disable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr = __raw_readw(FRQCR);
frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
/* enable standby */
stbcr = ctrl_inb(STBCR);
ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
stbcr = __raw_readb(STBCR);
__raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
/* set self-refresh */
mcr = ctrl_inw(MCR);
ctrl_outw(mcr & ~MCR_RFSH, MCR);
mcr = __raw_readw(MCR);
__raw_writew(mcr & ~MCR_RFSH, MCR);
/* set interrupt handler */
asm volatile("stc vbr, %0" : "=r" (vbr_old));
@ -73,8 +73,8 @@ static void pm_enter(void)
&wakeup_start, &wakeup_end - &wakeup_start);
asm volatile("ldc %0, vbr" : : "r" (vbr_new));
ctrl_outw(0, RTCNT);
ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR);
__raw_writew(0, RTCNT);
__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
cpu_sleep();
@ -83,14 +83,14 @@ static void pm_enter(void)
free_page(vbr_new);
/* enable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr = __raw_readw(FRQCR);
frqcr |= FRQCR_PSTBY;
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
udelay(50);
frqcr |= FRQCR_PLLEN;
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
ctrl_outb(stbcr, STBCR);
__raw_writeb(stbcr, STBCR);
clear_bl_bit();
}
@ -115,21 +115,21 @@ static int hp6x0_pm_enter(suspend_state_t state)
outw(hd64461_stbcr, HD64461_STBCR);
#endif
ctrl_outb(0x1f, DACR);
__raw_writeb(0x1f, DACR);
stbcr = ctrl_inb(STBCR);
ctrl_outb(0x01, STBCR);
stbcr = __raw_readb(STBCR);
__raw_writeb(0x01, STBCR);
stbcr2 = ctrl_inb(STBCR2);
ctrl_outb(0x7f , STBCR2);
stbcr2 = __raw_readb(STBCR2);
__raw_writeb(0x7f , STBCR2);
outw(0xf07f, HD64461_SCPUCR);
pm_enter();
outw(0, HD64461_SCPUCR);
ctrl_outb(stbcr, STBCR);
ctrl_outb(stbcr2, STBCR2);
__raw_writeb(stbcr, STBCR);
__raw_writeb(stbcr2, STBCR2);
#ifdef CONFIG_HD64461_ENABLER
hd64461_stbcr = inw(HD64461_STBCR);

12
arch/sh/boards/mach-hp6xx/setup.c
View File

@ -149,19 +149,19 @@ static void __init hp6xx_setup(char **cmdline_p)
sh_dac_output(0, DAC_SPEAKER_VOLUME);
sh_dac_disable(DAC_SPEAKER_VOLUME);
v8 = ctrl_inb(DACR);
v8 = __raw_readb(DACR);
v8 &= ~DACR_DAE;
ctrl_outb(v8,DACR);
__raw_writeb(v8,DACR);
v8 = ctrl_inb(SCPDR);
v8 = __raw_readb(SCPDR);
v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
v8 &= ~SCPDR_TS_SCAN_ENABLE;
ctrl_outb(v8, SCPDR);
__raw_writeb(v8, SCPDR);
v = ctrl_inw(SCPCR);
v = __raw_readw(SCPCR);
v &= ~SCPCR_TS_MASK;
v |= SCPCR_TS_ENABLE;
ctrl_outw(v, SCPCR);
__raw_writew(v, SCPCR);
}
device_initcall(hp6xx_devices_setup);

16
arch/sh/boards/mach-kfr2r09/setup.c
View File

@ -282,7 +282,7 @@ static int camera_power(struct device *dev, int mode)
* use 1.8 V for VccQ_VIO
* use 2.85V for VccQ_SR
*/
ctrl_outw((ctrl_inw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
__raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
/* reset clear */
ret = gpio_request(GPIO_PTB4, NULL);
@ -351,7 +351,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 101,
.start = 100,
.flags = IORESOURCE_IRQ,
},
};
@ -492,13 +492,13 @@ static int kfr2r09_usb0_gadget_setup(void)
if (kfr2r09_usb0_gadget_i2c_setup() != 0)
return -ENODEV; /* unable to configure using i2c */
ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
msleep(20); /* wait 20ms to let the clock settle */
clk_enable(clk_get(NULL, "usb0"));
ctrl_outw(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa40501d4);
return 0;
}
@ -526,12 +526,12 @@ static int __init kfr2r09_devices_setup(void)
gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
/* setup NOR flash at CS0 */
ctrl_outl(0x36db0400, BSC_CS0BCR);
ctrl_outl(0x00000500, BSC_CS0WCR);
__raw_writel(0x36db0400, BSC_CS0BCR);
__raw_writel(0x00000500, BSC_CS0WCR);
/* setup NAND flash at CS4 */
ctrl_outl(0x36db0400, BSC_CS4BCR);
ctrl_outl(0x00000500, BSC_CS4WCR);
__raw_writel(0x36db0400, BSC_CS4BCR);
__raw_writel(0x00000500, BSC_CS4WCR);
/* setup KEYSC pins */
gpio_request(GPIO_FN_KEYOUT0, NULL);

12
arch/sh/boards/mach-landisk/gio.c
View File

@ -76,39 +76,39 @@ static long gio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
break;
case GIODRV_IOCSGIODATA1: /* write byte */
ctrl_outb((unsigned char)(0x0ff & data), addr);
__raw_writeb((unsigned char)(0x0ff & data), addr);
break;
case GIODRV_IOCSGIODATA2: /* write word */
if (addr & 0x01) {
return -EFAULT;
}
ctrl_outw((unsigned short int)(0x0ffff & data), addr);
__raw_writew((unsigned short int)(0x0ffff & data), addr);
break;
case GIODRV_IOCSGIODATA4: /* write long */
if (addr & 0x03) {
return -EFAULT;
}
ctrl_outl(data, addr);
__raw_writel(data, addr);
break;
case GIODRV_IOCGGIODATA1: /* read byte */
data = ctrl_inb(addr);
data = __raw_readb(addr);
break;
case GIODRV_IOCGGIODATA2: /* read word */
if (addr & 0x01) {
return -EFAULT;
}
data = ctrl_inw(addr);
data = __raw_readw(addr);
break;
case GIODRV_IOCGGIODATA4: /* read long */
if (addr & 0x03) {
return -EFAULT;
}
data = ctrl_inl(addr);
data = __raw_readl(addr);
break;
default:
return -EFAULT;

6
arch/sh/boards/mach-landisk/irq.c
View File

@ -22,14 +22,14 @@ static void disable_landisk_irq(unsigned int irq)
{
unsigned char mask = 0xff ^ (0x01 << (irq - 5));
ctrl_outb(ctrl_inb(PA_IMASK) & mask, PA_IMASK);
__raw_writeb(__raw_readb(PA_IMASK) & mask, PA_IMASK);
}
static void enable_landisk_irq(unsigned int irq)
{
unsigned char value = (0x01 << (irq - 5));
ctrl_outb(ctrl_inb(PA_IMASK) | value, PA_IMASK);
__raw_writeb(__raw_readb(PA_IMASK) | value, PA_IMASK);
}
static struct irq_chip landisk_irq_chip __read_mostly = {
@ -52,5 +52,5 @@ void __init init_landisk_IRQ(void)
handle_level_irq, "level");
enable_landisk_irq(i);
}
ctrl_outb(0x00, PA_PWRINT_CLR);
__raw_writeb(0x00, PA_PWRINT_CLR);
}

4
arch/sh/boards/mach-landisk/psw.c
View File

@ -25,7 +25,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
unsigned int sw_value;
int ret = 0;
sw_value = (0x0ff & (~ctrl_inb(PA_STATUS)));
sw_value = (0x0ff & (~__raw_readb(PA_STATUS)));
/* Nothing to do if there's no state change */
if (psw->state) {
@ -42,7 +42,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
out:
/* Clear the switch IRQs */
ctrl_outb(0x00, PA_PWRINT_CLR);
__raw_writeb(0x00, PA_PWRINT_CLR);
return IRQ_RETVAL(ret);
}

6
arch/sh/boards/mach-landisk/setup.c
View File

@ -25,7 +25,7 @@ void init_landisk_IRQ(void);
static void landisk_power_off(void)
{
ctrl_outb(0x01, PA_SHUTDOWN);
__raw_writeb(0x01, PA_SHUTDOWN);
}
static struct resource cf_ide_resources[3];
@ -63,7 +63,7 @@ static int __init landisk_devices_setup(void)
/* open I/O area window */
paddrbase = virt_to_phys((void *)PA_AREA5_IO);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot);
cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
if (!cf_ide_base) {
printk("allocate_cf_area : can't open CF I/O window!\n");
return -ENOMEM;
@ -88,7 +88,7 @@ __initcall(landisk_devices_setup);
static void __init landisk_setup(char **cmdline_p)
{
/* LED ON */
ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED);
__raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
pm_power_off = landisk_power_off;

4
arch/sh/boards/mach-lboxre2/setup.c
View File

@ -56,8 +56,8 @@ static int __init lboxre2_devices_setup(void)
/* open I/O area window */
paddrbase = virt_to_phys((void*)PA_AREA5_IO);
psize = PAGE_SIZE;
prot = PAGE_KERNEL_PCC( 1 , _PAGE_PCC_IO16);
cf0_io_base = (u32)p3_ioremap(paddrbase, psize, prot.pgprot);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf0_io_base = (u32)ioremap_prot(paddrbase, psize, pgprot_val(prot));
if (!cf0_io_base) {
printk(KERN_ERR "%s : can't open CF I/O window!\n" , __func__ );
return -ENOMEM;

4
arch/sh/boards/mach-microdev/io.c
View File

@ -141,10 +141,10 @@ static inline void delay(void)
#if defined(CONFIG_PCI)
/* System board present, just make a dummy SRAM access. (CS0 will be
mapped to PCI memory, probably good to avoid it.) */
ctrl_inw(0xa6800000);
__raw_readw(0xa6800000);
#else
/* CS0 will be mapped to flash, ROM etc so safe to access it. */
ctrl_inw(0xa0000000);
__raw_readw(0xa0000000);
#endif
}

10
arch/sh/boards/mach-microdev/irq.c
View File

@ -88,7 +88,7 @@ static void disable_microdev_irq(unsigned int irq)
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
/* disable interrupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
}
static void enable_microdev_irq(unsigned int irq)
@ -107,13 +107,13 @@ static void enable_microdev_irq(unsigned int irq)
priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
/* set priority for the interrupt */
priorities = ctrl_inl(priorityReg);
priorities = __raw_readl(priorityReg);
priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
ctrl_outl(priorities, priorityReg);
__raw_writel(priorities, priorityReg);
/* enable interrupts on the FPGA INTC register */
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
}
/* This function sets the desired irq handler to be a MicroDev type */
@ -134,7 +134,7 @@ extern void __init init_microdev_irq(void)
int i;
/* disable interrupts on the FPGA INTC register */
ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
__raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
make_microdev_irq(i);

22
arch/sh/boards/mach-migor/setup.c
View File

@ -397,7 +397,7 @@ static struct resource sdhi_cn9_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 101,
.start = 100,
.flags = IORESOURCE_IRQ,
},
};
@ -496,28 +496,16 @@ static int __init migor_devices_setup(void)
&migor_sdram_enter_end,
&migor_sdram_leave_start,
&migor_sdram_leave_end);
#ifdef CONFIG_PM
/* Let D11 LED show STATUS0 */
gpio_request(GPIO_FN_STATUS0, NULL);
/* Lit D12 LED show PDSTATUS */
gpio_request(GPIO_FN_PDSTATUS, NULL);
#else
/* Lit D11 LED */
gpio_request(GPIO_PTJ7, NULL);
gpio_direction_output(GPIO_PTJ7, 1);
gpio_export(GPIO_PTJ7, 0);
/* Lit D12 LED */
gpio_request(GPIO_PTJ5, NULL);
gpio_direction_output(GPIO_PTJ5, 1);
gpio_export(GPIO_PTJ5, 0);
#endif
/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
gpio_request(GPIO_FN_IRQ0, NULL);
ctrl_outl(0x00003400, BSC_CS4BCR);
ctrl_outl(0x00110080, BSC_CS4WCR);
__raw_writel(0x00003400, BSC_CS4BCR);
__raw_writel(0x00110080, BSC_CS4WCR);
/* KEYSC */
gpio_request(GPIO_FN_KEYOUT0, NULL);
@ -533,7 +521,7 @@ static int __init migor_devices_setup(void)
/* NAND Flash */
gpio_request(GPIO_FN_CS6A_CE2B, NULL);
ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
gpio_request(GPIO_PTA1, NULL);
gpio_direction_input(GPIO_PTA1);
@ -627,7 +615,7 @@ static int __init migor_devices_setup(void)
#else
gpio_direction_output(GPIO_PTT0, 1);
#endif
ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

4
arch/sh/boards/mach-r2d/irq.c
View File

@ -129,7 +129,7 @@ void __init init_rts7751r2d_IRQ(void)
{
struct intc_desc *d;
switch (ctrl_inw(PA_VERREG) & 0xf0) {
switch (__raw_readw(PA_VERREG) & 0xf0) {
#ifdef CONFIG_RTS7751R2D_PLUS
case 0x10:
printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
@ -147,7 +147,7 @@ void __init init_rts7751r2d_IRQ(void)
#endif
default:
printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n",
ctrl_inw(PA_VERREG));
__raw_readw(PA_VERREG));
return;
}

8
arch/sh/boards/mach-r2d/setup.c
View File

@ -70,7 +70,7 @@ static struct spi_board_info spi_bus[] = {
static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state)
{
BUG_ON(cs != 0); /* Single Epson RTC-9701JE attached on CS0 */
ctrl_outw(state == BITBANG_CS_ACTIVE, PA_RTCCE);
__raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
}
static struct sh_spi_info spi_info = {
@ -262,7 +262,7 @@ __initcall(rts7751r2d_devices_setup);
static void rts7751r2d_power_off(void)
{
ctrl_outw(0x0001, PA_POWOFF);
__raw_writew(0x0001, PA_POWOFF);
}
/*
@ -271,14 +271,14 @@ static void rts7751r2d_power_off(void)
static void __init rts7751r2d_setup(char **cmdline_p)
{
void __iomem *sm501_reg;
u16 ver = ctrl_inw(PA_VERREG);
u16 ver = __raw_readw(PA_VERREG);
printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
printk(KERN_INFO "FPGA version:%d (revision:%d)\n",
(ver >> 4) & 0xf, ver & 0xf);
ctrl_outw(0x0000, PA_OUTPORT);
__raw_writew(0x0000, PA_OUTPORT);
pm_power_off = rts7751r2d_power_off;
/* sm501 dram configuration:

2
arch/sh/boards/mach-rsk/devices-rsk7203.c
View File

@ -96,7 +96,7 @@ static int __init rsk7203_devices_setup(void)
gpio_request(GPIO_FN_RXD0, NULL);
/* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
ctrl_outl(0x36db0400, 0xfffc0008); /* CS1BCR */
__raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
gpio_request(GPIO_FN_IRQ0_PB, NULL);
return platform_add_devices(rsk7203_devices,

4
arch/sh/boards/mach-sdk7780/irq.c
View File

@ -37,9 +37,9 @@ void __init init_sdk7780_IRQ(void)
{
printk(KERN_INFO "Using SDK7780 interrupt controller.\n");
ctrl_outw(0xFFFF, FPGA_IRQ0MR);
__raw_writew(0xFFFF, FPGA_IRQ0MR);
/* Setup IRL 0-3 */
ctrl_outw(0x0003, FPGA_IMSR);
__raw_writew(0x0003, FPGA_IMSR);
plat_irq_setup_pins(IRQ_MODE_IRL3210);
register_intc_controller(&fpga_intc_desc);

29
arch/sh/boards/mach-sdk7780/setup.c
View File

@ -20,27 +20,18 @@
#define GPIO_PECR 0xFFEA0008
//* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
/* Heartbeat */
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
@ -83,8 +74,8 @@ device_initcall(sdk7780_devices_setup);
static void __init sdk7780_setup(char **cmdline_p)
{
u16 ver = ctrl_inw(FPGA_FPVERR);
u16 dateStamp = ctrl_inw(FPGA_FPDATER);
u16 ver = __raw_readw(FPGA_FPVERR);
u16 dateStamp = __raw_readw(FPGA_FPDATER);
printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n");
printk(KERN_INFO "Board version: %d (revision %d), "
@ -94,7 +85,7 @@ static void __init sdk7780_setup(char **cmdline_p)
dateStamp);
/* Setup pin mux'ing for PCIC */
ctrl_outw(0x0000, GPIO_PECR);
__raw_writew(0x0000, GPIO_PECR);
}
/*

1
arch/sh/boards/mach-sdk7786/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y := setup.o fpga.o irq.o

72
arch/sh/boards/mach-sdk7786/fpga.c Normal file
View File

@ -0,0 +1,72 @@
/*
* SDK7786 FPGA Support.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bcd.h>
#include <mach/fpga.h>
#include <asm/sizes.h>
#define FPGA_REGS_OFFSET 0x03fff800
#define FPGA_REGS_SIZE 0x490
/*
* The FPGA can be mapped in any of the generally available areas,
* so we attempt to scan for it using the fixed SRSTR read magic.
*
* Once the FPGA is located, the rest of the mapping data for the other
* components can be determined dynamically from its section mapping
* registers.
*/
static void __iomem *sdk7786_fpga_probe(void)
{
unsigned long area;
void __iomem *base;
/*
* Iterate over all of the areas where the FPGA could be mapped.
* The possible range is anywhere from area 0 through 6, area 7
* is reserved.
*/
for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
if (!base) {
/* Failed to remap this area, move along. */
continue;
}
if (ioread16(base + SRSTR) == SRSTR_MAGIC)
return base; /* Found it! */
iounmap(base);
}
return NULL;
}
void __iomem *sdk7786_fpga_base;
void __init sdk7786_fpga_init(void)
{
u16 version, date;
sdk7786_fpga_base = sdk7786_fpga_probe();
if (unlikely(!sdk7786_fpga_base)) {
panic("FPGA detection failed.\n");
return;
}
version = fpga_read_reg(FPGAVR);
date = fpga_read_reg(FPGADR);
pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
((date >> 12) & 0xf) + 2000,
(date >> 8) & 0xf, bcd2bin(date & 0xff));
}

48
arch/sh/boards/mach-sdk7786/irq.c Normal file
View File

@ -0,0 +1,48 @@
/*
* SDK7786 FPGA IRQ Controller Support.
*
* Copyright (C) 2010 Matt Fleming
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/irq.h>
#include <mach/fpga.h>
#include <mach/irq.h>
enum {
ATA_IRQ_BIT = 1,
SPI_BUSY_BIT = 2,
LIRQ5_BIT = 3,
LIRQ6_BIT = 4,
LIRQ7_BIT = 5,
LIRQ8_BIT = 6,
KEY_IRQ_BIT = 7,
PEN_IRQ_BIT = 8,
ETH_IRQ_BIT = 9,
RTC_ALARM_BIT = 10,
CRYSTAL_FAIL_BIT = 12,
ETH_PME_BIT = 14,
};
void __init sdk7786_init_irq(void)
{
unsigned int tmp;
/* Enable priority encoding for all IRLs */
fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
/* Clear FPGA interrupt status registers */
fpga_write_reg(0x0000, INTASR);
fpga_write_reg(0x0000, INTBSR);
/* Unmask FPGA interrupts */
tmp = fpga_read_reg(INTAMR);
tmp &= ~(1 << ETH_IRQ_BIT);
fpga_write_reg(tmp, INTAMR);
plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
}

189
arch/sh/boards/mach-sdk7786/setup.c Normal file
View File

@ -0,0 +1,189 @@
/*
* Renesas Technology Europe SDK7786 Support.
*
* Copyright (C) 2010 Matt Fleming
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <mach/fpga.h>
#include <mach/irq.h>
#include <asm/machvec.h>
#include <asm/heartbeat.h>
#include <asm/sizes.h>
#include <asm/reboot.h>
static struct resource heartbeat_resource = {
.start = 0x07fff8b0,
.end = 0x07fff8b0 + sizeof(u16) - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct resource smsc911x_resources[] = {
[0] = {
.name = "smsc911x-memory",
.start = 0x07ffff00,
.end = 0x07ffff00 + SZ_256 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "smsc911x-irq",
.start = evt2irq(0x2c0),
.end = evt2irq(0x2c0),
.flags = IORESOURCE_IRQ,
},
};
static struct smsc911x_platform_config smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_32BIT,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct resource smbus_fpga_resource = {
.start = 0x07fff9e0,
.end = 0x07fff9e0 + SZ_32 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device smbus_fpga_device = {
.name = "i2c-sdk7786",
.id = 0,
.num_resources = 1,
.resource = &smbus_fpga_resource,
};
static struct resource smbus_pcie_resource = {
.start = 0x07fffc30,
.end = 0x07fffc30 + SZ_32 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device smbus_pcie_device = {
.name = "i2c-sdk7786",
.id = 1,
.num_resources = 1,
.resource = &smbus_pcie_resource,
};
static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
{
I2C_BOARD_INFO("max6900", 0x68),
},
};
static struct platform_device *sh7786_devices[] __initdata = {
&heartbeat_device,
&smsc911x_device,
&smbus_fpga_device,
&smbus_pcie_device,
};
static int sdk7786_i2c_setup(void)
{
unsigned int tmp;
/*
* Hand over I2C control to the FPGA.
*/
tmp = fpga_read_reg(SBCR);
tmp &= ~SCBR_I2CCEN;
tmp |= SCBR_I2CMEN;
fpga_write_reg(tmp, SBCR);
return i2c_register_board_info(0, sdk7786_i2c_devices,
ARRAY_SIZE(sdk7786_i2c_devices));
}
static int __init sdk7786_devices_setup(void)
{
int ret;
ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
if (unlikely(ret != 0))
return ret;
return sdk7786_i2c_setup();
}
__initcall(sdk7786_devices_setup);
static int sdk7786_mode_pins(void)
{
return fpga_read_reg(MODSWR);
}
static int sdk7786_clk_init(void)
{
struct clk *clk;
int ret;
/*
* Only handle the EXTAL case, anyone interfacing a crystal
* resonator will need to provide their own input clock.
*/
if (test_mode_pin(MODE_PIN9))
return -EINVAL;
clk = clk_get(NULL, "extal");
if (!clk || IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
return ret;
}
static void sdk7786_restart(char *cmd)
{
fpga_write_reg(0xa5a5, SRSTR);
}
/* Initialize the board */
static void __init sdk7786_setup(char **cmdline_p)
{
pr_info("Renesas Technology Europe SDK7786 support:\n");
sdk7786_fpga_init();
pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
machine_ops.restart = sdk7786_restart;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_sdk7786 __initmv = {
.mv_name = "SDK7786",
.mv_setup = sdk7786_setup,
.mv_mode_pins = sdk7786_mode_pins,
.mv_clk_init = sdk7786_clk_init,
.mv_init_irq = sdk7786_init_irq,
};

2
arch/sh/boards/mach-se/7206/io.c
View File

@ -16,7 +16,7 @@
static inline void delay(void)
{
ctrl_inw(0x20000000); /* P2 ROM Area */
__raw_readw(0x20000000); /* P2 ROM Area */
}
/* MS7750 requires special versions of in*, out* routines, since

43
arch/sh/boards/mach-se/7206/irq.c
View File

@ -32,12 +32,12 @@ static void disable_se7206_irq(unsigned int irq)
unsigned short msk0,msk1;
/* Set the priority in IPR to 0 */
val = ctrl_inw(INTC_IPR01);
val = __raw_readw(INTC_IPR01);
val &= mask;
ctrl_outw(val, INTC_IPR01);
__raw_writew(val, INTC_IPR01);
/* FPGA mask set */
msk0 = ctrl_inw(INTMSK0);
msk1 = ctrl_inw(INTMSK1);
msk0 = __raw_readw(INTMSK0);
msk1 = __raw_readw(INTMSK1);
switch (irq) {
case IRQ0_IRQ:
@ -51,8 +51,8 @@ static void disable_se7206_irq(unsigned int irq)
msk1 |= 0x00ff;
break;
}
ctrl_outw(msk0, INTMSK0);
ctrl_outw(msk1, INTMSK1);
__raw_writew(msk0, INTMSK0);
__raw_writew(msk1, INTMSK1);
}
static void enable_se7206_irq(unsigned int irq)
@ -62,13 +62,13 @@ static void enable_se7206_irq(unsigned int irq)
unsigned short msk0,msk1;
/* Set priority in IPR back to original value */
val = ctrl_inw(INTC_IPR01);
val = __raw_readw(INTC_IPR01);
val |= value;
ctrl_outw(val, INTC_IPR01);
__raw_writew(val, INTC_IPR01);
/* FPGA mask reset */
msk0 = ctrl_inw(INTMSK0);
msk1 = ctrl_inw(INTMSK1);
msk0 = __raw_readw(INTMSK0);
msk1 = __raw_readw(INTMSK1);
switch (irq) {
case IRQ0_IRQ:
@ -82,19 +82,20 @@ static void enable_se7206_irq(unsigned int irq)
msk1 &= ~0x00ff;
break;
}
ctrl_outw(msk0, INTMSK0);
ctrl_outw(msk1, INTMSK1);
__raw_writew(msk0, INTMSK0);
__raw_writew(msk1, INTMSK1);
}
static void eoi_se7206_irq(unsigned int irq)
{
unsigned short sts0,sts1;
struct irq_desc *desc = irq_to_desc(irq);
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_se7206_irq(irq);
/* FPGA isr clear */
sts0 = ctrl_inw(INTSTS0);
sts1 = ctrl_inw(INTSTS1);
sts0 = __raw_readw(INTSTS0);
sts1 = __raw_readw(INTSTS1);
switch (irq) {
case IRQ0_IRQ:
@ -108,8 +109,8 @@ static void eoi_se7206_irq(unsigned int irq)
sts1 &= ~0x00ff;
break;
}
ctrl_outw(sts0, INTSTS0);
ctrl_outw(sts1, INTSTS1);
__raw_writew(sts0, INTSTS0);
__raw_writew(sts1, INTSTS1);
}
static struct irq_chip se7206_irq_chip __read_mostly = {
@ -136,11 +137,11 @@ void __init init_se7206_IRQ(void)
make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
make_se7206_irq(IRQ1_IRQ); /* ATA */
make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
__raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
/* FPGA System register setup*/
ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */
ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */
__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
ctrl_outw(0x0001,INTSEL);
__raw_writew(0x0001,INTSEL);
}

15
arch/sh/boards/mach-se/7206/setup.c
View File

@ -50,15 +50,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 32,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
};
static struct platform_device heartbeat_device = {
@ -67,8 +64,8 @@ static struct platform_device heartbeat_device = {
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct platform_device *se7206_devices[] __initdata = {

45
arch/sh/boards/mach-se/7343/irq.c
View File

@ -16,16 +16,18 @@
#include <linux/io.h>
#include <mach-se/mach/se7343.h>
unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
static void disable_se7343_irq(unsigned int irq)
{
unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
unsigned int bit = (unsigned int)get_irq_chip_data(irq);
__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
}
static void enable_se7343_irq(unsigned int irq)
{
unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
unsigned int bit = (unsigned int)get_irq_chip_data(irq);
__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
}
static struct irq_chip se7343_irq_chip __read_mostly = {
@ -37,19 +39,16 @@ static struct irq_chip se7343_irq_chip __read_mostly = {
static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
{
unsigned short intv = ctrl_inw(PA_CPLD_ST);
struct irq_desc *ext_desc;
unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
unsigned short intv = __raw_readw(PA_CPLD_ST);
unsigned int ext_irq = 0;
intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
while (intv) {
if (intv & 1) {
ext_desc = irq_desc + ext_irq;
handle_level_irq(ext_irq, ext_desc);
}
intv >>= 1;
ext_irq++;
for (; intv; intv >>= 1, ext_irq++) {
if (!(intv & 1))
continue;
generic_handle_irq(se7343_fpga_irq[ext_irq]);
}
}
@ -58,16 +57,24 @@ static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
*/
void __init init_7343se_IRQ(void)
{
int i;
int i, irq;
ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
__raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
irq = create_irq();
if (irq < 0)
return;
se7343_fpga_irq[i] = irq;
set_irq_chip_and_handler_name(se7343_fpga_irq[i],
&se7343_irq_chip,
handle_level_irq, "level");
set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
}
set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);

43
arch/sh/boards/mach-se/7343/setup.c
View File

@ -11,26 +11,17 @@
#include <asm/irq.h>
#include <asm/io.h>
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct mtd_partition nor_flash_partitions[] = {
@ -82,7 +73,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
.mapbase = 0x16000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.irq = UARTA_IRQ,
.uartclk = 7372800,
},
[1] = {
@ -90,7 +80,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
.mapbase = 0x17000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.irq = UARTB_IRQ,
.uartclk = 7372800,
},
{ },
@ -121,7 +110,7 @@ static struct resource usb_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
.start = USB_IRQ,
/* Filled in later */
.flags = IORESOURCE_IRQ,
},
};
@ -138,8 +127,8 @@ static struct isp116x_platform_data usb_platform_data = {
static struct platform_device usb_device = {
.name = "isp116x-hcd",
.id = -1,
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
.dev = {
.platform_data = &usb_platform_data,
},
@ -155,6 +144,13 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
static int __init sh7343se_devices_setup(void)
{
/* Wire-up dynamic vectors */
serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
usb_resources[2].start = usb_resources[2].end =
se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
return platform_add_devices(sh7343se_platform_devices,
ARRAY_SIZE(sh7343se_platform_devices));
}
@ -165,10 +161,10 @@ device_initcall(sh7343se_devices_setup);
*/
static void __init sh7343se_setup(char **cmdline_p)
{
ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
__raw_writew(0xf900, FPGA_OUT); /* FPGA */
ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
ctrl_outw(0x0020, PORT_PSELD);
__raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
__raw_writew(0x0020, PORT_PSELD);
printk(KERN_INFO "MS7343CP01 Setup...done\n");
}
@ -179,6 +175,5 @@ static void __init sh7343se_setup(char **cmdline_p)
static struct sh_machine_vector mv_7343se __initmv = {
.mv_name = "SolutionEngine 7343",
.mv_setup = sh7343se_setup,
.mv_nr_irqs = SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_NR,
.mv_init_irq = init_7343se_IRQ,
};

14
arch/sh/boards/mach-se/770x/irq.c
View File

@ -96,13 +96,13 @@ static struct ipr_desc ipr_irq_desc = {
void __init init_se_IRQ(void)
{
/* Disable all interrupts */
ctrl_outw(0, BCR_ILCRA);
ctrl_outw(0, BCR_ILCRB);
ctrl_outw(0, BCR_ILCRC);
ctrl_outw(0, BCR_ILCRD);
ctrl_outw(0, BCR_ILCRE);
ctrl_outw(0, BCR_ILCRF);
ctrl_outw(0, BCR_ILCRG);
__raw_writew(0, BCR_ILCRA);
__raw_writew(0, BCR_ILCRB);
__raw_writew(0, BCR_ILCRC);
__raw_writew(0, BCR_ILCRD);
__raw_writew(0, BCR_ILCRE);
__raw_writew(0, BCR_ILCRF);
__raw_writew(0, BCR_ILCRG);
register_ipr_controller(&ipr_irq_desc);
}

15
arch/sh/boards/mach-se/770x/setup.c
View File

@ -93,15 +93,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
@ -110,8 +107,8 @@ static struct platform_device heartbeat_device = {
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\

2
arch/sh/boards/mach-se/7721/irq.c
View File

@ -38,7 +38,7 @@ static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
void __init init_se7721_IRQ(void)
{
/* PPCR */
ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118);
__raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118);
register_intc_controller(&intc_desc);
intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);

23
arch/sh/boards/mach-se/7721/setup.c
View File

@ -23,15 +23,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
@ -40,8 +37,8 @@ static struct platform_device heartbeat_device = {
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct resource cf_ide_resources[] = {
@ -83,10 +80,10 @@ device_initcall(se7721_devices_setup);
static void __init se7721_setup(char **cmdline_p)
{
/* for USB */
ctrl_outw(0x0000, 0xA405010C); /* PGCR */
ctrl_outw(0x0000, 0xA405010E); /* PHCR */
ctrl_outw(0x00AA, 0xA4050118); /* PPCR */
ctrl_outw(0x0000, 0xA4050124); /* PSELA */
__raw_writew(0x0000, 0xA405010C); /* PGCR */
__raw_writew(0x0000, 0xA405010E); /* PHCR */
__raw_writew(0x00AA, 0xA4050118); /* PPCR */
__raw_writew(0x0000, 0xA4050124); /* PSELA */
}
/*

10
arch/sh/boards/mach-se/7722/irq.c
View File

@ -21,13 +21,13 @@ unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
static void disable_se7722_irq(unsigned int irq)
{
unsigned int bit = (unsigned int)get_irq_chip_data(irq);
ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
__raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
}
static void enable_se7722_irq(unsigned int irq)
{
unsigned int bit = (unsigned int)get_irq_chip_data(irq);
ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
__raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
}
static struct irq_chip se7722_irq_chip __read_mostly = {
@ -39,7 +39,7 @@ static struct irq_chip se7722_irq_chip __read_mostly = {
static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
{
unsigned short intv = ctrl_inw(IRQ01_STS);
unsigned short intv = __raw_readw(IRQ01_STS);
unsigned int ext_irq = 0;
intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
@ -59,8 +59,8 @@ void __init init_se7722_IRQ(void)
{
int i, irq;
ctrl_outw(0, IRQ01_MASK); /* disable all irqs */
ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
__raw_writew(0, IRQ01_MASK); /* disable all irqs */
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
irq = create_irq();

55
arch/sh/boards/mach-se/7722/setup.c
View File

@ -25,26 +25,17 @@
#include <cpu/sh7722.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
@ -165,32 +156,32 @@ device_initcall(se7722_devices_setup);
static void __init se7722_setup(char **cmdline_p)
{
ctrl_outw(0x010D, FPGA_OUT); /* FPGA */
__raw_writew(0x010D, FPGA_OUT); /* FPGA */
ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
__raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
__raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
/* LCDC I/O */
ctrl_outw(0x0020, PORT_PSELD);
__raw_writew(0x0020, PORT_PSELD);
/* SIOF1*/
ctrl_outw(0x0003, PORT_PSELB);
ctrl_outw(0xe000, PORT_PSELC);
ctrl_outw(0x0000, PORT_PKCR);
__raw_writew(0x0003, PORT_PSELB);
__raw_writew(0xe000, PORT_PSELC);
__raw_writew(0x0000, PORT_PKCR);
/* LCDC */
ctrl_outw(0x4020, PORT_PHCR);
ctrl_outw(0x0000, PORT_PLCR);
ctrl_outw(0x0000, PORT_PMCR);
ctrl_outw(0x0002, PORT_PRCR);
ctrl_outw(0x0000, PORT_PXCR); /* LCDC,CS6A */
__raw_writew(0x4020, PORT_PHCR);
__raw_writew(0x0000, PORT_PLCR);
__raw_writew(0x0000, PORT_PMCR);
__raw_writew(0x0002, PORT_PRCR);
__raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
/* KEYSC */
ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
ctrl_outw(0x0000, PORT_PYCR);
ctrl_outw(0x0000, PORT_PZCR);
ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
__raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
__raw_writew(0x0000, PORT_PYCR);
__raw_writew(0x0000, PORT_PZCR);
__raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
__raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
}
/*

58
arch/sh/boards/mach-se/7724/irq.c
View File

@ -72,14 +72,14 @@ static void disable_se7724_irq(unsigned int irq)
{
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
__raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
}
static void enable_se7724_irq(unsigned int irq)
{
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
__raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
}
static struct irq_chip se7724_irq_chip __read_mostly = {
@ -92,19 +92,16 @@ static struct irq_chip se7724_irq_chip __read_mostly = {
static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
{
struct fpga_irq set = get_fpga_irq(irq);
unsigned short intv = ctrl_inw(set.sraddr);
struct irq_desc *ext_desc;
unsigned short intv = __raw_readw(set.sraddr);
unsigned int ext_irq = set.base;
intv &= set.mask;
while (intv) {
if (intv & 0x0001) {
ext_desc = irq_desc + ext_irq;
handle_level_irq(ext_irq, ext_desc);
}
intv >>= 1;
ext_irq++;
for (; intv; intv >>= 1, ext_irq++) {
if (!(intv & 1))
continue;
generic_handle_irq(ext_irq);
}
}
@ -113,20 +110,39 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
*/
void __init init_se7724_IRQ(void)
{
int i;
int i, nid = cpu_to_node(boot_cpu_data);
ctrl_outw(0xffff, IRQ0_MR); /* mask all */
ctrl_outw(0xffff, IRQ1_MR); /* mask all */
ctrl_outw(0xffff, IRQ2_MR); /* mask all */
ctrl_outw(0x0000, IRQ0_SR); /* clear irq */
ctrl_outw(0x0000, IRQ1_SR); /* clear irq */
ctrl_outw(0x0000, IRQ2_SR); /* clear irq */
ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
__raw_writew(0xffff, IRQ0_MR); /* mask all */
__raw_writew(0xffff, IRQ1_MR); /* mask all */
__raw_writew(0xffff, IRQ2_MR); /* mask all */
__raw_writew(0x0000, IRQ0_SR); /* clear irq */
__raw_writew(0x0000, IRQ1_SR); /* clear irq */
__raw_writew(0x0000, IRQ2_SR); /* clear irq */
__raw_writew(0x002a, IRQ_MODE); /* set irq type */
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) {
int irq, wanted;
wanted = SE7724_FPGA_IRQ_BASE + i;
irq = create_irq_nr(wanted, nid);
if (unlikely(irq == 0)) {
pr_err("%s: failed hooking irq %d for FPGA\n",
__func__, wanted);
return;
}
if (unlikely(irq != wanted)) {
pr_err("%s: got irq %d but wanted %d, bailing.\n",
__func__, irq, wanted);
destroy_irq(irq);
return;
}
set_irq_chip_and_handler_name(irq,
&se7724_irq_chip,
handle_level_irq, "level");
}
set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);

79
arch/sh/boards/mach-se/7724/sdram.S
View File

@ -39,6 +39,10 @@ ENTRY(ms7724se_sdram_leave_start)
/* DBSC: put memory in auto-refresh mode */
mov.l @(SH_SLEEP_MODE, r5), r0
tst #SUSP_SH_RSTANDBY, r0
bf resume_rstandby
ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
WAIT 1
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
@ -49,4 +53,79 @@ ENTRY(ms7724se_sdram_leave_start)
rts
nop
resume_rstandby:
/* CPG: setup clocks before restarting external memory */
ED 0xA4150024, 0x00004000 /* PLLCR */
mov.l FRQCRA,r0
mov.l @r0,r3
mov.l KICK,r1
or r1, r3
mov.l r3, @r0
mov.l LSTATS,r0
mov #1,r1
WAIT_LSTATS:
mov.l @r0,r3
tst r1,r3
bf WAIT_LSTATS
/* DBSC: re-initialize and put in auto-refresh */
ED 0xFD000108, 0x00000181 /* DBPDCNT0 */
ED 0xFD000020, 0x015B0002 /* DBCONF */
ED 0xFD000030, 0x03071502 /* DBTR0 */
ED 0xFD000034, 0x02020102 /* DBTR1 */
ED 0xFD000038, 0x01090405 /* DBTR2 */
ED 0xFD00003C, 0x00000002 /* DBTR3 */
ED 0xFD000008, 0x00000005 /* DBKIND */
ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
ED 0xFD000018, 0x00000001 /* DBCKECNT */
mov #100,r0
WAIT_400NS:
dt r0
bf WAIT_400NS
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */
ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */
ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */
ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */
ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */
ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */
mov #100,r0
WAIT_400NS_2:
dt r0
bf WAIT_400NS_2
ED 0xFD000010, 0x00000001 /* DBEN */
ED 0xFD000044, 0x0000050f /* DBRFPDN1 */
ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */
mov.l DUMMY,r0
mov.l @r0, r1 /* force single dummy read */
ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
ED 0xFD000108, 0x00000080 /* DBPDCNT0 */
ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
rts
nop
.balign 4
DUMMY: .long 0xac400000
FRQCRA: .long 0xa4150000
KICK: .long 0x80000000
LSTATS: .long 0xa4150060
ENTRY(ms7724se_sdram_leave_end)

114
arch/sh/boards/mach-se/7724/setup.c
View File

@ -53,26 +53,17 @@
*/
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* LAN91C111 */
@ -265,12 +256,12 @@ static struct platform_device ceu1_device = {
#define FCLKACR 0xa4150008
static void fsimck_init(struct clk *clk)
{
u32 status = ctrl_inl(clk->enable_reg);
u32 status = __raw_readl(clk->enable_reg);
/* use external clock */
status &= ~0x000000ff;
status |= 0x00000080;
ctrl_outl(status, clk->enable_reg);
__raw_writel(status, clk->enable_reg);
}
static struct clk_ops fsimck_clk_ops = {
@ -322,7 +313,7 @@ static struct platform_device fsi_device = {
/* KEYSC in SoC (Needs SW33-2 set to ON) */
static struct sh_keysc_info keysc_info = {
.mode = SH_KEYSC_MODE_1,
.scan_timing = 10,
.scan_timing = 3,
.delay = 50,
.keycodes = {
KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
@ -460,7 +451,7 @@ static struct resource sdhi0_cn7_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 101,
.start = 100,
.flags = IORESOURCE_IRQ,
},
};
@ -483,7 +474,7 @@ static struct resource sdhi1_cn8_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 24,
.start = 23,
.flags = IORESOURCE_IRQ,
},
};
@ -498,6 +489,26 @@ static struct platform_device sdhi1_cn8_device = {
},
};
/* IrDA */
static struct resource irda_resources[] = {
[0] = {
.name = "IrDA",
.start = 0xA45D0000,
.end = 0xA45D0049,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device irda_device = {
.name = "sh_sir",
.num_resources = ARRAY_SIZE(irda_resources),
.resource = irda_resources,
};
static struct platform_device *ms7724se_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
@ -512,6 +523,7 @@ static struct platform_device *ms7724se_devices[] __initdata = {
&fsi_device,
&sdhi0_cn7_device,
&sdhi1_cn8_device,
&irda_device,
};
/* I2C device */
@ -531,7 +543,7 @@ static int __init sh_eth_is_eeprom_ready(void)
int t = 10000;
while (t--) {
if (!ctrl_inw(EEPROM_STAT))
if (!__raw_readw(EEPROM_STAT))
return 1;
udelay(1);
}
@ -551,13 +563,13 @@ static void __init sh_eth_init(void)
/* read MAC addr from EEPROM */
for (i = 0 ; i < 3 ; i++) {
ctrl_outw(0x0, EEPROM_OP); /* read */
ctrl_outw(i*2, EEPROM_ADR);
ctrl_outw(0x1, EEPROM_STRT);
__raw_writew(0x0, EEPROM_OP); /* read */
__raw_writew(i*2, EEPROM_ADR);
__raw_writew(0x1, EEPROM_STRT);
if (!sh_eth_is_eeprom_ready())
return;
mac = ctrl_inw(EEPROM_DATA);
mac = __raw_readw(EEPROM_DATA);
sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
}
@ -594,28 +606,29 @@ arch_initcall(arch_setup);
static int __init devices_setup(void)
{
u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
struct clk *fsia_clk;
u16 sw = __raw_readw(SW4140); /* select camera, monitor */
struct clk *clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&ms7724se_sdram_enter_start,
&ms7724se_sdram_enter_end,
&ms7724se_sdram_leave_start,
&ms7724se_sdram_leave_end);
/* Reset Release */
ctrl_outw(ctrl_inw(FPGA_OUT) &
__raw_writew(__raw_readw(FPGA_OUT) &
~((1 << 1) | /* LAN */
(1 << 6) | /* VIDEO DAC */
(1 << 7) | /* AK4643 */
(1 << 8) | /* IrDA */
(1 << 12) | /* USB0 */
(1 << 14)), /* RMII */
FPGA_OUT);
/* turn on USB clocks, use external clock */
ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
#ifdef CONFIG_PM
/* Let LED9 show STATUS2 */
gpio_request(GPIO_FN_STATUS2, NULL);
@ -624,28 +637,12 @@ static int __init devices_setup(void)
/* Lit LED11 show PDSTATUS */
gpio_request(GPIO_FN_PDSTATUS, NULL);
#else
/* Lit LED9 */
gpio_request(GPIO_PTJ6, NULL);
gpio_direction_output(GPIO_PTJ6, 1);
gpio_export(GPIO_PTJ6, 0);
/* Lit LED10 */
gpio_request(GPIO_PTJ5, NULL);
gpio_direction_output(GPIO_PTJ5, 1);
gpio_export(GPIO_PTJ5, 0);
/* Lit LED11 */
gpio_request(GPIO_PTJ7, NULL);
gpio_direction_output(GPIO_PTJ7, 1);
gpio_export(GPIO_PTJ7, 0);
#endif
/* enable USB0 port */
ctrl_outw(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa40501d4);
/* enable USB1 port */
ctrl_outw(0x0600, 0xa4050192);
__raw_writew(0x0600, 0xa4050192);
/* enable IRQ 0,1,2 */
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
@ -693,7 +690,7 @@ static int __init devices_setup(void)
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDRD, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
@ -764,13 +761,18 @@ static int __init devices_setup(void)
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
gpio_request(GPIO_FN_FSIIASD, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
/* change parent of FSI A */
fsia_clk = clk_get(NULL, "fsia_clk");
clk = clk_get(NULL, "fsia_clk");
clk_register(&fsimcka_clk);
clk_set_parent(fsia_clk, &fsimcka_clk);
clk_set_rate(fsia_clk, 11000);
clk_set_parent(clk, &fsimcka_clk);
clk_set_rate(clk, 11000);
clk_set_rate(&fsimcka_clk, 11000);
clk_put(fsia_clk);
clk_put(clk);
/* SDHI0 connected to cn7 */
gpio_request(GPIO_FN_SDHI0CD, NULL);
@ -792,6 +794,10 @@ static int __init devices_setup(void)
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
/*
* enable SH-Eth
*

18
arch/sh/boards/mach-se/7780/irq.c
View File

@ -24,30 +24,30 @@
void __init init_se7780_IRQ(void)
{
/* enable all interrupt at FPGA */
ctrl_outw(0, FPGA_INTMSK1);
__raw_writew(0, FPGA_INTMSK1);
/* mask SM501 interrupt */
ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
__raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
/* enable all interrupt at FPGA */
ctrl_outw(0, FPGA_INTMSK2);
__raw_writew(0, FPGA_INTMSK2);
/* set FPGA INTSEL register */
/* FPGA + 0x06 */
ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) |
__raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
/* FPGA + 0x08 */
ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
__raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
/* FPGA + 0x0A */
ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
__raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
/* ICR1: detect low level(for 2ndcut) */
ctrl_outl(0xAAAA0000, INTC_ICR1);
__raw_writel(0xAAAA0000, INTC_ICR1);
/*
* FPGA PCISEL register initialize
@ -63,6 +63,6 @@ void __init init_se7780_IRQ(void)
* INTD || INTD | INTC | -- | INTA
* -------------------------------------
*/
ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
__raw_writew(0x0013, FPGA_PCI_INTSEL1);
__raw_writew(0xE402, FPGA_PCI_INTSEL2);
}

47
arch/sh/boards/mach-se/7780/setup.c
View File

@ -17,26 +17,17 @@
#include <asm/heartbeat.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
@ -84,14 +75,14 @@ device_initcall(se7780_devices_setup);
static void __init se7780_setup(char **cmdline_p)
{
/* "SH-Linux" on LED Display */
ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
__raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
__raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
__raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
__raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
__raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
__raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
__raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
__raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
@ -102,15 +93,15 @@ static void __init se7780_setup(char **cmdline_p)
* REQ2/GNT2 -> Serial ATA
* REQ3/GNT3 -> PCI slot
*/
ctrl_outw(0x0213, FPGA_REQSEL);
__raw_writew(0x0213, FPGA_REQSEL);
/* GPIO setting */
ctrl_outw(0x0000, GPIO_PECR);
ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
ctrl_outw(0x0c00, GPIO_PMSELR);
__raw_writew(0x0000, GPIO_PECR);
__raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
__raw_writew(0x0c00, GPIO_PMSELR);
/* iVDR Power ON */
ctrl_outw(0x0001, FPGA_IVDRPW);
__raw_writew(0x0001, FPGA_IVDRPW);
}
/*

50
arch/sh/boards/mach-sh03/rtc.c
View File

@ -44,15 +44,15 @@ unsigned long get_cmos_time(void)
spin_lock(&sh03_rtc_lock);
again:
do {
sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10;
min = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10;
hour = (ctrl_inb(RTC_HOU1) & 0xf) + (ctrl_inb(RTC_HOU10) & 0xf) * 10;
day = (ctrl_inb(RTC_DAY1) & 0xf) + (ctrl_inb(RTC_DAY10) & 0xf) * 10;
mon = (ctrl_inb(RTC_MON1) & 0xf) + (ctrl_inb(RTC_MON10) & 0xf) * 10;
year = (ctrl_inb(RTC_YEA1) & 0xf) + (ctrl_inb(RTC_YEA10) & 0xf) * 10
+ (ctrl_inb(RTC_YEA100 ) & 0xf) * 100
+ (ctrl_inb(RTC_YEA1000) & 0xf) * 1000;
} while (sec != (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10);
sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10;
min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10;
day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10;
mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10;
year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10
+ (__raw_readb(RTC_YEA100 ) & 0xf) * 100
+ (__raw_readb(RTC_YEA1000) & 0xf) * 1000;
} while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10);
if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
hour > 23 || min > 59 || sec > 59) {
printk(KERN_ERR
@ -60,16 +60,16 @@ unsigned long get_cmos_time(void)
printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n",
year, mon, day, hour, min, sec);
ctrl_outb(0, RTC_SEC1); ctrl_outb(0, RTC_SEC10);
ctrl_outb(0, RTC_MIN1); ctrl_outb(0, RTC_MIN10);
ctrl_outb(0, RTC_HOU1); ctrl_outb(0, RTC_HOU10);
ctrl_outb(6, RTC_WEE1);
ctrl_outb(1, RTC_DAY1); ctrl_outb(0, RTC_DAY10);
ctrl_outb(1, RTC_MON1); ctrl_outb(0, RTC_MON10);
ctrl_outb(0, RTC_YEA1); ctrl_outb(0, RTC_YEA10);
ctrl_outb(0, RTC_YEA100);
ctrl_outb(2, RTC_YEA1000);
ctrl_outb(0, RTC_CTL);
__raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10);
__raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10);
__raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10);
__raw_writeb(6, RTC_WEE1);
__raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10);
__raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10);
__raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10);
__raw_writeb(0, RTC_YEA100);
__raw_writeb(2, RTC_YEA1000);
__raw_writeb(0, RTC_CTL);
goto again;
}
@ -93,9 +93,9 @@ static int set_rtc_mmss(unsigned long nowtime)
/* gets recalled with irq locally disabled */
spin_lock(&sh03_rtc_lock);
for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
if (!(ctrl_inb(RTC_CTL) & RTC_BUSY))
if (!(__raw_readb(RTC_CTL) & RTC_BUSY))
break;
cmos_minutes = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10;
cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
@ -103,10 +103,10 @@ static int set_rtc_mmss(unsigned long nowtime)
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
ctrl_outb(real_seconds % 10, RTC_SEC1);
ctrl_outb(real_seconds / 10, RTC_SEC10);
ctrl_outb(real_minutes % 10, RTC_MIN1);
ctrl_outb(real_minutes / 10, RTC_MIN10);
__raw_writeb(real_seconds % 10, RTC_SEC1);
__raw_writeb(real_seconds / 10, RTC_SEC10);
__raw_writeb(real_minutes % 10, RTC_MIN1);
__raw_writeb(real_minutes / 10, RTC_MIN10);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",

2
arch/sh/boards/mach-sh03/setup.c
View File

@ -82,7 +82,7 @@ static int __init sh03_devices_setup(void)
/* open I/O area window */
paddrbase = virt_to_phys((void *)PA_AREA5_IO);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot);
cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
if (!cf_ide_base) {
printk("allocate_cf_area : can't open CF I/O window!\n");
return -ENOMEM;

10
arch/sh/boards/mach-sh7763rdp/irq.c
View File

@ -28,18 +28,18 @@
void __init init_sh7763rdp_IRQ(void)
{
/* GPIO enabled */
ctrl_outl(1 << 25, INTC_INT2MSKCR);
__raw_writel(1 << 25, INTC_INT2MSKCR);
/* enable GPIO interrupts */
ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
__raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
INTC_INT2PRI7);
/* USBH enabled */
ctrl_outl(1 << 17, INTC_INT2MSKCR1);
__raw_writel(1 << 17, INTC_INT2MSKCR1);
/* GETHER enabled */
ctrl_outl(1 << 16, INTC_INT2MSKCR1);
__raw_writel(1 << 16, INTC_INT2MSKCR1);
/* DMAC enabled */
ctrl_outl(1 << 8, INTC_INT2MSKCR);
__raw_writel(1 << 8, INTC_INT2MSKCR);
}

40
arch/sh/boards/mach-sh7763rdp/setup.c
View File

@ -158,50 +158,50 @@ device_initcall(sh7763rdp_devices_setup);
static void __init sh7763rdp_setup(char **cmdline_p)
{
/* Board version check */
if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
printk(KERN_INFO "RTE Standard Configuration\n");
else
printk(KERN_INFO "RTA Standard Configuration\n");
/* USB pin select bits (clear bit 5-2 to 0) */
ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
__raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
/* USBH setup port I controls to other (clear bits 4-9 to 0) */
ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR);
__raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
/* Select USB Host controller */
ctrl_outw(0x00, USB_USBHSC);
__raw_writew(0x00, USB_USBHSC);
/* For LCD */
/* set PTJ7-1, bits 15-2 of PJCR to 0 */
ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR);
__raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
/* set PTI5, bits 11-10 of PICR to 0 */
ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR);
ctrl_outw(0, PORT_PKCR);
ctrl_outw(0, PORT_PLCR);
__raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
__raw_writew(0, PORT_PKCR);
__raw_writew(0, PORT_PLCR);
/* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
__raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
/* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
__raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
/* For HAC */
/* bit3-0 0100:HAC & SSI1 enable */
ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
__raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
/* bit14 1:SSI_HAC_CLK enable */
ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
__raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
/* SH-Ether */
ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
ctrl_outw(0x0, PORT_PFCR);
ctrl_outw(0x0, PORT_PFCR);
ctrl_outw(0x0, PORT_PFCR);
__raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
__raw_writew(0x0, PORT_PFCR);
__raw_writew(0x0, PORT_PFCR);
__raw_writew(0x0, PORT_PFCR);
/* MMC */
/*selects SCIF and MMC other functions */
ctrl_outw(0x0001, PORT_PSEL0);
__raw_writew(0x0001, PORT_PSEL0);
/* MMC clock operates */
ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1);
ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR);
ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
__raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
__raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);
__raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
}
static struct sh_machine_vector mv_sh7763rdp __initmv = {

2
arch/sh/boards/mach-snapgear/setup.c
View File

@ -30,7 +30,7 @@
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
{
(void)ctrl_inb(0xb8000000); /* dummy read */
(void)__raw_readb(0xb8000000); /* dummy read */
printk("SnapGear: erase switch interrupt!\n");

12
arch/sh/boards/mach-systemh/irq.c
View File

@ -41,13 +41,13 @@ static void disable_systemh_irq(unsigned int irq)
unsigned long val, mask = 0x01 << 1;
/* Clear the "irq"th bit in the mask and set it in the request */
val = ctrl_inl((unsigned long)systemh_irq_mask_register);
val = __raw_readl((unsigned long)systemh_irq_mask_register);
val &= ~mask;
ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
__raw_writel(val, (unsigned long)systemh_irq_mask_register);
val = ctrl_inl((unsigned long)systemh_irq_request_register);
val = __raw_readl((unsigned long)systemh_irq_request_register);
val |= mask;
ctrl_outl(val, (unsigned long)systemh_irq_request_register);
__raw_writel(val, (unsigned long)systemh_irq_request_register);
}
}
@ -57,9 +57,9 @@ static void enable_systemh_irq(unsigned int irq)
unsigned long val, mask = 0x01 << 1;
/* Set "irq"th bit in the mask register */
val = ctrl_inl((unsigned long)systemh_irq_mask_register);
val = __raw_readl((unsigned long)systemh_irq_mask_register);
val |= mask;
ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
__raw_writel(val, (unsigned long)systemh_irq_mask_register);
}
}

5
arch/sh/boards/mach-titan/Makefile
View File

@ -1,5 +0,0 @@
#
# Makefile for the Nimble Microsystems TITAN specific parts of the kernel
#
obj-y := setup.o io.o

108
arch/sh/boards/mach-titan/io.c
View File

@ -1,108 +0,0 @@
/*
* I/O routines for Titan
*/
#include <linux/pci.h>
#include <asm/machvec.h>
#include <asm/addrspace.h>
#include <mach/titan.h>
#include <asm/io.h>
static inline unsigned int port2adr(unsigned int port)
{
maybebadio((unsigned long)port);
return port;
}
u8 titan_inb(unsigned long port)
{
if (PXSEG(port))
return ctrl_inb(port);
return ctrl_inw(port2adr(port)) & 0xff;
}
u8 titan_inb_p(unsigned long port)
{
u8 v;
if (PXSEG(port))
v = ctrl_inb(port);
else
v = ctrl_inw(port2adr(port)) & 0xff;
ctrl_delay();
return v;
}
u16 titan_inw(unsigned long port)
{
if (PXSEG(port))
return ctrl_inw(port);
else if (port >= 0x2000)
return ctrl_inw(port2adr(port));
else
maybebadio(port);
return 0;
}
u32 titan_inl(unsigned long port)
{
if (PXSEG(port))
return ctrl_inl(port);
else if (port >= 0x2000)
return ctrl_inw(port2adr(port));
else
maybebadio(port);
return 0;
}
void titan_outb(u8 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else
ctrl_outw(value, port2adr(port));
}
void titan_outb_p(u8 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else
ctrl_outw(value, port2adr(port));
ctrl_delay();
}
void titan_outw(u16 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outw(value, port);
else if (port >= 0x2000)
ctrl_outw(value, port2adr(port));
else
maybebadio(port);
}
void titan_outl(u32 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outl(value, port);
else
maybebadio(port);
}
void titan_insl(unsigned long port, void *dst, unsigned long count)
{
maybebadio(port);
}
void titan_outsl(unsigned long port, const void *src, unsigned long count)
{
maybebadio(port);
}
void __iomem *titan_ioport_map(unsigned long port, unsigned int size)
{
if (PXSEG(port))
return (void __iomem *)port;
return (void __iomem *)port2adr(port);
}

8
arch/sh/boards/mach-x3proto/ilsel.c
View File

@ -70,10 +70,10 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n",
__func__, bit, addr, shift, set);
tmp = ctrl_inw(addr);
tmp = __raw_readw(addr);
tmp &= ~(0xf << shift);
tmp |= set << shift;
ctrl_outw(tmp, addr);
__raw_writew(tmp, addr);
}
/**
@ -142,9 +142,9 @@ void ilsel_disable(unsigned int irq)
addr = mk_ilsel_addr(irq);
tmp = ctrl_inw(addr);
tmp = __raw_readw(addr);
tmp &= ~(0xf << mk_ilsel_shift(irq));
ctrl_outw(tmp, addr);
__raw_writew(tmp, addr);
clear_bit(irq, &ilsel_level_map);
}

2
arch/sh/boards/mach-x3proto/setup.c
View File

@ -149,7 +149,7 @@ static void __init x3proto_init_irq(void)
plat_irq_setup_pins(IRQ_MODE_IRL3210);
/* Set ICR0.LVLMODE */
ctrl_outl(ctrl_inl(0xfe410000) | (1 << 21), 0xfe410000);
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
}
static struct sh_machine_vector mv_x3proto __initmv = {

28
arch/sh/boot/Makefile
View File

@ -21,12 +21,15 @@ CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000
CONFIG_ENTRY_OFFSET ?= 0x00001000
suffix-y := bin
suffix-$(CONFIG_KERNEL_GZIP) := gz
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
suffix-$(CONFIG_KERNEL_LZMA) := lzma
suffix-$(CONFIG_KERNEL_GZIP) := gz
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
suffix-$(CONFIG_KERNEL_LZMA) := lzma
suffix-$(CONFIG_KERNEL_LZO) := lzo
targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz uImage.bz2 uImage.lzma uImage.bin
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz \
uImage.bz2 uImage.lzma uImage.lzo uImage.bin
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
vmlinux.bin.lzo
subdir- := compressed romimage
$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
@ -43,15 +46,8 @@ $(obj)/romImage: $(obj)/romimage/vmlinux FORCE
$(obj)/romimage/vmlinux: $(obj)/zImage FORCE
$(Q)$(MAKE) $(build)=$(obj)/romimage $@
KERNEL_MEMORY := 0x00000000
ifeq ($(CONFIG_PMB_FIXED),y)
KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
$$[$(CONFIG_MEMORY_START) & 0x1fffffff]')
endif
ifeq ($(CONFIG_29BIT),y)
KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
$$[$(CONFIG_MEMORY_START)]')
endif
KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
$$[$(CONFIG_PAGE_OFFSET) + \
@ -80,6 +76,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzma)
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzo)
$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
$(call if_changed,uimage,bzip2)
@ -89,6 +88,9 @@ $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
$(call if_changed,uimage,lzma)
$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
$(call if_changed,uimage,lzo)
$(obj)/uImage.bin: $(obj)/vmlinux.bin
$(call if_changed,uimage,none)

7
arch/sh/boot/compressed/Makefile
View File

@ -6,14 +6,11 @@
targets := vmlinux vmlinux.bin vmlinux.bin.gz \
vmlinux.bin.bz2 vmlinux.bin.lzma \
vmlinux.bin.lzo \
head_$(BITS).o misc.o piggy.o
OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
ifdef CONFIG_SH_STANDARD_BIOS
OBJECTS += $(obj)/../../kernel/sh_bios.o
endif
#
# IMAGE_OFFSET is the load offset of the compression loader
#
@ -47,6 +44,8 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE
$(call if_changed,bzip2)
$(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE
$(call if_changed,lzma)
$(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE
$(call if_changed,lzo)
OBJCOPYFLAGS += -R .empty_zero_page

23
arch/sh/boot/compressed/misc.c
View File

@ -14,7 +14,6 @@
#include <asm/uaccess.h>
#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/sh_bios.h>
/*
* gzip declarations
@ -62,29 +61,15 @@ static unsigned long free_mem_end_ptr;
#include "../../../../lib/decompress_unlzma.c"
#endif
#ifdef CONFIG_SH_STANDARD_BIOS
size_t strlen(const char *s)
{
int i = 0;
#ifdef CONFIG_KERNEL_LZO
#include "../../../../lib/decompress_unlzo.c"
#endif
while (*s++)
i++;
return i;
}
int puts(const char *s)
{
int len = strlen(s);
sh_bios_console_write(s, len);
return len;
}
#else
int puts(const char *s)
{
/* This should be updated to use the sh-sci routines */
return 0;
}
#endif
void* memset(void* s, int c, size_t n)
{
@ -132,7 +117,7 @@ void decompress_kernel(void)
output_addr = (CONFIG_MEMORY_START + 0x2000);
#else
output_addr = __pa((unsigned long)&_text+PAGE_SIZE);
#ifdef CONFIG_29BIT
#if defined(CONFIG_29BIT)
output_addr |= P2SEG;
#endif
#endif

36
arch/sh/cchips/hd6446x/hd64461.c
View File

@ -55,25 +55,22 @@ static struct irq_chip hd64461_irq_chip = {
static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
{
unsigned short intv = ctrl_inw(HD64461_NIRR);
struct irq_desc *ext_desc;
unsigned short intv = __raw_readw(HD64461_NIRR);
unsigned int ext_irq = HD64461_IRQBASE;
intv &= (1 << HD64461_IRQ_NUM) - 1;
while (intv) {
if (intv & 1) {
ext_desc = irq_desc + ext_irq;
handle_level_irq(ext_irq, ext_desc);
}
intv >>= 1;
ext_irq++;
for (; intv; intv >>= 1, ext_irq++) {
if (!(intv & 1))
continue;
generic_handle_irq(ext_irq);
}
}
int __init setup_hd64461(void)
{
int i;
int i, nid = cpu_to_node(boot_cpu_data);
if (!MACH_HD64461)
return 0;
@ -90,9 +87,26 @@ int __init setup_hd64461(void)
__raw_writew(0xffff, HD64461_NIMR);
/* IRQ 80 -> 95 belongs to HD64461 */
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
unsigned int irq;
irq = create_irq_nr(i, nid);
if (unlikely(irq == 0)) {
pr_err("%s: failed hooking irq %d for HD64461\n",
__func__, i);
return -EBUSY;
}
if (unlikely(irq != i)) {
pr_err("%s: got irq %d but wanted %d, bailing.\n",
__func__, irq, i);
destroy_irq(irq);
return -EINVAL;
}
set_irq_chip_and_handler(i, &hd64461_irq_chip,
handle_level_irq);
}
set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);

1754
arch/sh/configs/sdk7786_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

10
arch/sh/drivers/dma/dma-pvr2.c
View File

@ -40,10 +40,10 @@ static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
static int pvr2_request_dma(struct dma_channel *chan)
{
if (ctrl_inl(PVR2_DMA_MODE) != 0)
if (__raw_readl(PVR2_DMA_MODE) != 0)
return -EBUSY;
ctrl_outl(0, PVR2_DMA_LMMODE0);
__raw_writel(0, PVR2_DMA_LMMODE0);
return 0;
}
@ -60,9 +60,9 @@ static int pvr2_xfer_dma(struct dma_channel *chan)
xfer_complete = 0;
ctrl_outl(chan->dar, PVR2_DMA_ADDR);
ctrl_outl(chan->count, PVR2_DMA_COUNT);
ctrl_outl(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
__raw_writel(chan->dar, PVR2_DMA_ADDR);
__raw_writel(chan->count, PVR2_DMA_COUNT);
__raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
return 0;
}

31
arch/sh/drivers/dma/dma-sh.c
View File

@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
*
* iterations to complete the transfer.
*/
static unsigned int ts_shift[] = TS_SHIFT;
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
return ts_shift[cnt];
}
/*
@ -70,13 +73,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
struct dma_channel *chan = dev_id;
u32 chcr;
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
if (!(chcr & CHCR_TE))
return IRQ_NONE;
chcr &= ~(CHCR_IE | CHCR_DE);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
wake_up(&chan->wait_queue);
@ -115,7 +118,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
chan->flags &= ~DMA_TEI_CAPABLE;
}
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
chan->flags |= DMA_CONFIGURED;
return 0;
@ -126,13 +129,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
int irq;
u32 chcr;
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
chcr |= CHCR_DE;
if (chan->flags & DMA_TEI_CAPABLE)
chcr |= CHCR_IE;
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
if (chan->flags & DMA_TEI_CAPABLE) {
irq = get_dmte_irq(chan->chan);
@ -150,9 +153,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
disable_irq(irq);
}
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
}
static int sh_dmac_xfer_dma(struct dma_channel *chan)
@ -183,12 +186,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
*/
if (chan->sar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
__raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
if (chan->dar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
__raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
ctrl_outl(chan->count >> calc_xmit_shift(chan),
__raw_writel(chan->count >> calc_xmit_shift(chan),
(dma_base_addr[chan->chan] + TCR));
sh_dmac_enable_dma(chan);
@ -198,10 +201,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
static int sh_dmac_get_dma_residue(struct dma_channel *chan)
{
if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
return 0;
return ctrl_inl(dma_base_addr[chan->chan] + TCR)
return __raw_readl(dma_base_addr[chan->chan] + TCR)
<< calc_xmit_shift(chan);
}

22
arch/sh/drivers/dma/dmabrg.c
View File

@ -86,8 +86,8 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
unsigned long dcr;
unsigned int i;
dcr = ctrl_inl(DMABRGCR);
ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
dcr = __raw_readl(DMABRGCR);
__raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
dcr &= dcr >> 8; /* ignore masked */
/* USB stuff, get it out of the way first */
@ -109,17 +109,17 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
static void dmabrg_disable_irq(unsigned int dmairq)
{
unsigned long dcr;
dcr = ctrl_inl(DMABRGCR);
dcr = __raw_readl(DMABRGCR);
dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
ctrl_outl(dcr, DMABRGCR);
__raw_writel(dcr, DMABRGCR);
}
static void dmabrg_enable_irq(unsigned int dmairq)
{
unsigned long dcr;
dcr = ctrl_inl(DMABRGCR);
dcr = __raw_readl(DMABRGCR);
dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
ctrl_outl(dcr, DMABRGCR);
__raw_writel(dcr, DMABRGCR);
}
int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*),
@ -165,13 +165,13 @@ static int __init dmabrg_init(void)
printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n");
#endif
ctrl_outl(0, DMABRGCR);
ctrl_outl(0, DMACHCR0);
ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
__raw_writel(0, DMABRGCR);
__raw_writel(0, DMACHCR0);
__raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
/* enable DMABRG mode, enable the DMAC */
or = ctrl_inl(DMAOR);
ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
or = __raw_readl(DMAOR);
__raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED,
"DMABRG USB address error", NULL);

22
arch/sh/drivers/heartbeat.c
View File

@ -1,7 +1,7 @@
/*
* Generic heartbeat driver for regular LED banks
*
* Copyright (C) 2007 Paul Mundt
* Copyright (C) 2007 - 2010 Paul Mundt
*
* Most SH reference boards include a number of individual LEDs that can
* be independently controlled (either via a pre-defined hardware
@ -27,7 +27,7 @@
#include <asm/heartbeat.h>
#define DRV_NAME "heartbeat"
#define DRV_VERSION "0.1.1"
#define DRV_VERSION "0.1.2"
static unsigned char default_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
@ -98,7 +98,7 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
return -ENOMEM;
}
hd->base = ioremap_nocache(res->start, res->end - res->start + 1);
hd->base = ioremap_nocache(res->start, resource_size(res));
if (unlikely(!hd->base)) {
dev_err(&pdev->dev, "ioremap failed\n");
@ -117,8 +117,20 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
for (i = 0; i < hd->nr_bits; i++)
hd->mask |= (1 << hd->bit_pos[i]);
if (!hd->regsize)
hd->regsize = 8; /* default access size */
if (!hd->regsize) {
switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
case IORESOURCE_MEM_32BIT:
hd->regsize = 32;
break;
case IORESOURCE_MEM_16BIT:
hd->regsize = 16;
break;
case IORESOURCE_MEM_8BIT:
default:
hd->regsize = 8;
break;
}
}
setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd);
platform_set_drvdata(pdev, hd);

5
arch/sh/drivers/pci/Makefile
View File

@ -1,14 +1,14 @@
#
# Makefile for the PCI specific kernel interface routines under Linux.
#
obj-y += pci.o
obj-y += common.o pci.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += ops-sh7786.o
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o
obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
@ -25,4 +25,3 @@ obj-$(CONFIG_SH_TITAN) += fixups-titan.o
obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o
obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o
obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o
obj-$(CONFIG_SH_URQUELL) += pcie-sh7786.o

162
arch/sh/drivers/pci/common.c Normal file
View File

@ -0,0 +1,162 @@
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/kernel.h>
/*
* These functions are used early on before PCI scanning is done
* and all of the pci_dev and pci_bus structures have been created.
*/
static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
int top_bus, int busnr, int devfn)
{
static struct pci_dev dev;
static struct pci_bus bus;
dev.bus = &bus;
dev.sysdata = hose;
dev.devfn = devfn;
bus.number = busnr;
bus.sysdata = hose;
bus.ops = hose->pci_ops;
if(busnr != top_bus)
/* Fake a parent bus structure. */
bus.parent = &bus;
else
bus.parent = NULL;
return &dev;
}
#define EARLY_PCI_OP(rw, size, type) \
int __init early_##rw##_config_##size(struct pci_channel *hose, \
int top_bus, int bus, int devfn, int offset, type value) \
{ \
return pci_##rw##_config_##size( \
fake_pci_dev(hose, top_bus, bus, devfn), \
offset, value); \
}
EARLY_PCI_OP(read, byte, u8 *)
EARLY_PCI_OP(read, word, u16 *)
EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
int __init pci_is_66mhz_capable(struct pci_channel *hose,
int top_bus, int current_bus)
{
u32 pci_devfn;
unsigned short vid;
int cap66 = -1;
u16 stat;
printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn))
continue;
if (early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_VENDOR_ID, &vid) !=
PCIBIOS_SUCCESSFUL)
continue;
if (vid == 0xffff)
continue;
/* check 66MHz capability */
if (cap66 < 0)
cap66 = 1;
if (cap66) {
early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_STATUS, &stat);
if (!(stat & PCI_STATUS_66MHZ)) {
printk(KERN_DEBUG
"PCI: %02x:%02x not 66MHz capable.\n",
current_bus, pci_devfn);
cap66 = 0;
break;
}
}
}
return cap66 > 0;
}
static void pcibios_enable_err(unsigned long __data)
{
struct pci_channel *hose = (struct pci_channel *)__data;
del_timer(&hose->err_timer);
printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
enable_irq(hose->err_irq);
}
static void pcibios_enable_serr(unsigned long __data)
{
struct pci_channel *hose = (struct pci_channel *)__data;
del_timer(&hose->serr_timer);
printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
enable_irq(hose->serr_irq);
}
void pcibios_enable_timers(struct pci_channel *hose)
{
if (hose->err_irq) {
init_timer(&hose->err_timer);
hose->err_timer.data = (unsigned long)hose;
hose->err_timer.function = pcibios_enable_err;
}
if (hose->serr_irq) {
init_timer(&hose->serr_timer);
hose->serr_timer.data = (unsigned long)hose;
hose->serr_timer.function = pcibios_enable_serr;
}
}
/*
* A simple handler for the regular PCI status errors, called from IRQ
* context.
*/
unsigned int pcibios_handle_status_errors(unsigned long addr,
unsigned int status,
struct pci_channel *hose)
{
unsigned int cmd = 0;
if (status & PCI_STATUS_REC_MASTER_ABORT) {
printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
cmd |= PCI_STATUS_REC_MASTER_ABORT;
}
if (status & PCI_STATUS_REC_TARGET_ABORT) {
printk(KERN_DEBUG "PCI: target abort: ");
pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
PCI_STATUS_SIG_TARGET_ABORT |
PCI_STATUS_REC_MASTER_ABORT, 1);
printk("\n");
cmd |= PCI_STATUS_REC_TARGET_ABORT;
}
if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
printk(KERN_DEBUG "PCI: parity error detected: ");
pcibios_report_status(PCI_STATUS_PARITY |
PCI_STATUS_DETECTED_PARITY, 1);
printk("\n");
cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
/* Now back off of the IRQ for awhile */
if (hose->err_irq) {
disable_irq_nosync(hose->err_irq);
hose->err_timer.expires = jiffies + HZ;
add_timer(&hose->err_timer);
}
}
return cmd;
}

2
arch/sh/drivers/pci/fixups-dreamcast.c
View File

@ -39,7 +39,7 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
/*
* We also assume that dev->devfn == 0
*/
dev->resource[1].start = p->io_resource->start + 0x100;
dev->resource[1].start = p->resources[0].start + 0x100;
dev->resource[1].end = dev->resource[1].start + 0x200 - 1;
/*

12
arch/sh/drivers/pci/fixups-r7780rp.c
View File

@ -22,15 +22,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return irq_tab[slot];
}
int pci_fixup_pcic(struct pci_channel *chan)
{
pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
return 0;
}

4
arch/sh/drivers/pci/fixups-rts7751r2d.c
View File

@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
{
unsigned long bcr1, mcr;
bcr1 = ctrl_inl(SH7751_BCR1);
bcr1 = __raw_readl(SH7751_BCR1);
bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
pci_write_reg(chan, bcr1, SH4_PCIBCR1);
@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
mcr = ctrl_inl(SH7751_MCR);
mcr = __raw_readl(SH7751_MCR);
mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
pci_write_reg(chan, mcr, SH4_PCIMCR);

19
arch/sh/drivers/pci/fixups-sdk7780.c
View File

@ -31,22 +31,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return sdk7780_irq_tab[pin-1][slot];
}
int pci_fixup_pcic(struct pci_channel *chan)
{
/* Enable all interrupts, so we know what to fix */
pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
/* Set up standard PCI config registers */
pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
return 0;
}

6
arch/sh/drivers/pci/fixups-se7751.c
View File

@ -97,12 +97,12 @@ int pci_fixup_pcic(struct pci_channel *chan)
* meaning all calls go straight through... use BUG_ON to
* catch erroneous assumption.
*/
BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);
BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);
PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
/* Set IOBR for window containing area specified in pci.h */
PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));
PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
/* All done, may as well say so... */
printk("SH7751 PCI: Finished initialization of the PCI controller\n");

30
arch/sh/drivers/pci/ops-sh4.c
View File

@ -16,7 +16,7 @@
* Direct access to PCI hardware...
*/
#define CONFIG_CMD(bus, devfn, where) \
(P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
static DEFINE_SPINLOCK(sh4_pci_lock);
@ -102,34 +102,6 @@ struct pci_ops sh4_pci_ops = {
.write = sh4_pci_write,
};
/*
* Not really related to pci_ops, but it's common and not worth shoving
* somewhere else for now..
*/
int __init sh4_pci_check_direct(struct pci_channel *chan)
{
/*
* Check if configuration works.
*/
unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
pci_write_reg(chan, P1SEG, SH4_PCIPAR);
if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
pci_write_reg(chan, tmp, SH4_PCIPAR);
printk(KERN_INFO "PCI: Using configuration type 1\n");
request_region(chan->reg_base + SH4_PCIPAR, 8,
"PCI conf1");
return 0;
}
pci_write_reg(chan, tmp, SH4_PCIPAR);
printk(KERN_ERR "PCI: %s failed\n", __func__);
return -EINVAL;
}
int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
{
/* Nothing to do. */

32
arch/sh/drivers/pci/pci-dreamcast.c
View File

@ -25,25 +25,25 @@
#include <asm/irq.h>
#include <mach/pci.h>
static struct resource gapspci_io_resource = {
.name = "GAPSPCI IO",
.start = GAPSPCI_BBA_CONFIG,
.end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
.flags = IORESOURCE_IO,
};
static struct resource gapspci_mem_resource = {
.name = "GAPSPCI mem",
.start = GAPSPCI_DMA_BASE,
.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
.flags = IORESOURCE_MEM,
static struct resource gapspci_resources[] = {
{
.name = "GAPSPCI IO",
.start = GAPSPCI_BBA_CONFIG,
.end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
.flags = IORESOURCE_IO,
}, {
.name = "GAPSPCI mem",
.start = GAPSPCI_DMA_BASE,
.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct pci_channel dreamcast_pci_controller = {
.pci_ops = &gapspci_pci_ops,
.io_resource = &gapspci_io_resource,
.resources = gapspci_resources,
.nr_resources = ARRAY_SIZE(gapspci_resources),
.io_offset = 0x00000000,
.mem_resource = &gapspci_mem_resource,
.mem_offset = 0x00000000,
};
@ -95,8 +95,6 @@ static int __init gapspci_init(void)
outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
register_pci_controller(&dreamcast_pci_controller);
return 0;
return register_pci_controller(&dreamcast_pci_controller);
}
arch_initcall(gapspci_init);

18
arch/sh/drivers/pci/pci-sh4.h
View File

@ -49,6 +49,17 @@
#define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
#define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
#define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
#define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
#define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
#define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
#define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
#define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
#define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
#define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
#define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
#define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
#define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
#define SH4_PCIALR 0x11C /* Error Address Register */
#define SH4_PCICLR 0x120 /* Error Command/Data */
#define SH4_PCICLR_MPIO 0x80000000
@ -61,7 +72,7 @@
#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
#define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
#define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
#define SH4_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */
#define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
#define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
#define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
#define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
@ -151,7 +162,6 @@
/* arch/sh/kernel/drivers/pci/ops-sh4.c */
extern struct pci_ops sh4_pci_ops;
int sh4_pci_check_direct(struct pci_channel *chan);
int pci_fixup_pcic(struct pci_channel *chan);
struct sh4_pci_address_space {
@ -167,13 +177,13 @@ struct sh4_pci_address_map {
static inline void pci_write_reg(struct pci_channel *chan,
unsigned long val, unsigned long reg)
{
ctrl_outl(val, chan->reg_base + reg);
__raw_writel(val, chan->reg_base + reg);
}
static inline unsigned long pci_read_reg(struct pci_channel *chan,
unsigned long reg)
{
return ctrl_inl(chan->reg_base + reg);
return __raw_readl(chan->reg_base + reg);
}
#endif /* __PCI_SH4_H */

19
arch/sh/drivers/pci/pci-sh5.c
View File

@ -89,14 +89,13 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
return IRQ_NONE;
}
static struct resource sh5_io_resource = { /* place holder */ };
static struct resource sh5_mem_resource = { /* place holder */ };
static struct resource sh5_pci_resources[2];
static struct pci_channel sh5pci_controller = {
.pci_ops = &sh5_pci_ops,
.mem_resource = &sh5_mem_resource,
.resources = sh5_pci_resources,
.nr_resources = ARRAY_SIZE(sh5_pci_resources),
.mem_offset = 0x00000000,
.io_resource = &sh5_io_resource,
.io_offset = 0x00000000,
};
@ -210,14 +209,12 @@ static int __init sh5pci_init(void)
SH5PCI_WRITE(AINTM, ~0);
SH5PCI_WRITE(PINTM, ~0);
sh5_io_resource.start = PCI_IO_AREA;
sh5_io_resource.end = PCI_IO_AREA + 0x10000;
sh5_pci_resources[0].start = PCI_IO_AREA;
sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;
sh5_mem_resource.start = memStart;
sh5_mem_resource.end = memStart + memSize;
sh5_pci_resources[1].start = memStart;
sh5_pci_resources[1].end = memStart + memSize;
register_pci_controller(&sh5pci_controller);
return 0;
return register_pci_controller(&sh5pci_controller);
}
arch_initcall(sh5pci_init);

12
arch/sh/drivers/pci/pci-sh5.h
View File

@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
/* Write I/O functions */
#define SH5PCI_WRITE(reg,val) ctrl_outl((u32)(val),PCISH5_ICR_REG(reg))
#define SH5PCI_WRITE_SHORT(reg,val) ctrl_outw((u16)(val),PCISH5_ICR_REG(reg))
#define SH5PCI_WRITE_BYTE(reg,val) ctrl_outb((u8)(val),PCISH5_ICR_REG(reg))
#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
/* Read I/O functions */
#define SH5PCI_READ(reg) ctrl_inl(PCISH5_ICR_REG(reg))
#define SH5PCI_READ_SHORT(reg) ctrl_inw(PCISH5_ICR_REG(reg))
#define SH5PCI_READ_BYTE(reg) ctrl_inb(PCISH5_ICR_REG(reg))
#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg))
#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg))
#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg))
/* Set PCI config bits */
#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)

52
arch/sh/drivers/pci/pci-sh7751.c
View File

@ -44,25 +44,25 @@ static int __init __area_sdram_check(struct pci_channel *chan,
return 1;
}
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
static struct resource sh7751_pci_resources[] = {
{
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
}, {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
},
};
static struct pci_channel sh7751_pci_controller = {
.pci_ops = &sh4_pci_ops,
.mem_resource = &sh7751_mem_resource,
.resources = sh7751_pci_resources,
.nr_resources = ARRAY_SIZE(sh7751_pci_resources),
.mem_offset = 0x00000000,
.io_resource = &sh7751_io_resource,
.io_offset = 0x00000000,
.io_map_base = SH7751_PCI_IO_BASE,
};
@ -79,7 +79,6 @@ static int __init sh7751_pci_init(void)
struct pci_channel *chan = &sh7751_pci_controller;
unsigned int id;
u32 word, reg;
int ret;
printk(KERN_NOTICE "PCI: Starting intialization.\n");
@ -93,13 +92,10 @@ static int __init sh7751_pci_init(void)
return -ENODEV;
}
if ((ret = sh4_pci_check_direct(chan)) != 0)
return ret;
/* Set the BCR's to enable PCI access */
reg = ctrl_inl(SH7751_BCR1);
reg = __raw_readl(SH7751_BCR1);
reg |= 0x80000;
ctrl_outl(reg, SH7751_BCR1);
__raw_writel(reg, SH7751_BCR1);
/* Turn the clocks back on (not done in reset)*/
pci_write_reg(chan, 0, SH4_PCICLKR);
@ -132,13 +128,13 @@ static int __init sh7751_pci_init(void)
/* Set the local 16MB PCI memory space window to
* the lowest PCI mapped address
*/
word = chan->mem_resource->start & SH4_PCIMBR_MASK;
word = chan->resources[1].start & SH4_PCIMBR_MASK;
pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
pci_write_reg(chan, word , SH4_PCIMBR);
/* Make sure the MSB's of IO window are set to access PCI space
* correctly */
word = chan->io_resource->start & SH4_PCIIOBR_MASK;
word = chan->resources[0].start & SH4_PCIIOBR_MASK;
pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
pci_write_reg(chan, word, SH4_PCIIOBR);
@ -159,13 +155,13 @@ static int __init sh7751_pci_init(void)
return -1;
/* configure the wait control registers */
word = ctrl_inl(SH7751_WCR1);
word = __raw_readl(SH7751_WCR1);
pci_write_reg(chan, word, SH4_PCIWCR1);
word = ctrl_inl(SH7751_WCR2);
word = __raw_readl(SH7751_WCR2);
pci_write_reg(chan, word, SH4_PCIWCR2);
word = ctrl_inl(SH7751_WCR3);
word = __raw_readl(SH7751_WCR3);
pci_write_reg(chan, word, SH4_PCIWCR3);
word = ctrl_inl(SH7751_MCR);
word = __raw_readl(SH7751_MCR);
pci_write_reg(chan, word, SH4_PCIMCR);
/* NOTE: I'm ignoring the PCI error IRQs for now..
@ -180,8 +176,6 @@ static int __init sh7751_pci_init(void)
word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
pci_write_reg(chan, word, SH4_PCICR);
register_pci_controller(chan);
return 0;
return register_pci_controller(chan);
}
arch_initcall(sh7751_pci_init);

408
arch/sh/drivers/pci/pci-sh7780.c
View File

@ -1,7 +1,7 @@
/*
* Low-Level PCI Support for the SH7780
*
* Copyright (C) 2005 - 2009 Paul Mundt
* Copyright (C) 2005 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -11,52 +11,240 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/irq.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include "pci-sh4.h"
#include <asm/mmu.h>
#include <asm/sizes.h>
static struct resource sh7785_io_resource = {
.name = "SH7785_IO",
.start = SH7780_PCI_IO_BASE,
.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7785_mem_resource = {
.name = "SH7785_mem",
.start = SH7780_PCI_MEMORY_BASE,
.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
static struct resource sh7785_pci_resources[] = {
{
.name = "PCI IO",
.start = 0x1000,
.end = SZ_4M - 1,
.flags = IORESOURCE_IO,
}, {
.name = "PCI MEM 0",
.start = 0xfd000000,
.end = 0xfd000000 + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "PCI MEM 1",
.start = 0x10000000,
.end = 0x10000000 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
}, {
/*
* 32-bit only resources must be last.
*/
.name = "PCI MEM 2",
.start = 0xc0000000,
.end = 0xc0000000 + SZ_512M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
},
};
static struct pci_channel sh7780_pci_controller = {
.pci_ops = &sh4_pci_ops,
.mem_resource = &sh7785_mem_resource,
.mem_offset = 0x00000000,
.io_resource = &sh7785_io_resource,
.io_offset = 0x00000000,
.io_map_base = SH7780_PCI_IO_BASE,
.resources = sh7785_pci_resources,
.nr_resources = ARRAY_SIZE(sh7785_pci_resources),
.io_offset = 0,
.mem_offset = 0,
.io_map_base = 0xfe200000,
.serr_irq = evt2irq(0xa00),
.err_irq = evt2irq(0xaa0),
};
static struct sh4_pci_address_map sh7780_pci_map = {
.window0 = {
#if defined(CONFIG_32BIT)
.base = SH7780_32BIT_DDR_BASE_ADDR,
.size = 0x40000000,
#else
.base = SH7780_CS0_BASE_ADDR,
.size = 0x20000000,
#endif
},
struct pci_errors {
unsigned int mask;
const char *str;
} pci_arbiter_errors[] = {
{ SH4_PCIAINT_MBKN, "master broken" },
{ SH4_PCIAINT_TBTO, "target bus time out" },
{ SH4_PCIAINT_MBTO, "master bus time out" },
{ SH4_PCIAINT_TABT, "target abort" },
{ SH4_PCIAINT_MABT, "master abort" },
{ SH4_PCIAINT_RDPE, "read data parity error" },
{ SH4_PCIAINT_WDPE, "write data parity error" },
}, pci_interrupt_errors[] = {
{ SH4_PCIINT_MLCK, "master lock error" },
{ SH4_PCIINT_TABT, "target-target abort" },
{ SH4_PCIINT_TRET, "target retry time out" },
{ SH4_PCIINT_MFDE, "master function disable erorr" },
{ SH4_PCIINT_PRTY, "address parity error" },
{ SH4_PCIINT_SERR, "SERR" },
{ SH4_PCIINT_TWDP, "data parity error for target write" },
{ SH4_PCIINT_TRDP, "PERR detected for target read" },
{ SH4_PCIINT_MTABT, "target abort for master" },
{ SH4_PCIINT_MMABT, "master abort for master" },
{ SH4_PCIINT_MWPD, "master write data parity error" },
{ SH4_PCIINT_MRPD, "master read data parity error" },
};
static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
{
struct pci_channel *hose = dev_id;
unsigned long addr;
unsigned int status;
unsigned int cmd;
int i;
addr = __raw_readl(hose->reg_base + SH4_PCIALR);
/*
* Handle status errors.
*/
status = __raw_readw(hose->reg_base + PCI_STATUS);
if (status & (PCI_STATUS_PARITY |
PCI_STATUS_DETECTED_PARITY |
PCI_STATUS_SIG_TARGET_ABORT |
PCI_STATUS_REC_TARGET_ABORT |
PCI_STATUS_REC_MASTER_ABORT)) {
cmd = pcibios_handle_status_errors(addr, status, hose);
if (likely(cmd))
__raw_writew(cmd, hose->reg_base + PCI_STATUS);
}
/*
* Handle arbiter errors.
*/
status = __raw_readl(hose->reg_base + SH4_PCIAINT);
for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
if (status & pci_arbiter_errors[i].mask) {
printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
pci_arbiter_errors[i].str, addr);
cmd |= pci_arbiter_errors[i].mask;
}
}
__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
/*
* Handle the remaining PCI errors.
*/
status = __raw_readl(hose->reg_base + SH4_PCIINT);
for (i = cmd = 0; i < ARRAY_SIZE(pci_interrupt_errors); i++) {
if (status & pci_interrupt_errors[i].mask) {
printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
pci_interrupt_errors[i].str, addr);
cmd |= pci_interrupt_errors[i].mask;
}
}
__raw_writel(cmd, hose->reg_base + SH4_PCIINT);
return IRQ_HANDLED;
}
static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id)
{
struct pci_channel *hose = dev_id;
printk(KERN_DEBUG "PCI: system error received: ");
pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
printk("\n");
/* Deassert SERR */
__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
/* Back off the IRQ for awhile */
disable_irq_nosync(irq);
hose->serr_timer.expires = jiffies + HZ;
add_timer(&hose->serr_timer);
return IRQ_HANDLED;
}
static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
{
int ret;
/* Clear out PCI arbiter IRQs */
__raw_writel(0, hose->reg_base + SH4_PCIAINT);
/* Clear all error conditions */
__raw_writew(PCI_STATUS_DETECTED_PARITY | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_SIG_TARGET_ABORT | \
PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, IRQF_DISABLED,
"PCI SERR interrupt", hose);
if (unlikely(ret)) {
printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n");
return ret;
}
/*
* The PCI ERR IRQ needs to be IRQF_SHARED since all of the power
* down IRQ vectors are routed through the ERR IRQ vector. We
* only request_irq() once as there is only a single masking
* source for multiple events.
*/
ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
"PCI ERR interrupt", hose);
if (unlikely(ret)) {
free_irq(hose->serr_irq, hose);
return ret;
}
/* Unmask all of the arbiter IRQs. */
__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
/* Unmask all of the PCI IRQs */
__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
return ret;
}
static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
{
free_irq(hose->err_irq, hose);
free_irq(hose->serr_irq, hose);
}
static void __init sh7780_pci66_init(struct pci_channel *hose)
{
unsigned int tmp;
if (!pci_is_66mhz_capable(hose, 0, 0))
return;
/* Enable register access */
tmp = __raw_readl(hose->reg_base + SH4_PCICR);
tmp |= SH4_PCICR_PREFIX;
__raw_writel(tmp, hose->reg_base + SH4_PCICR);
/* Enable 66MHz operation */
tmp = __raw_readw(hose->reg_base + PCI_STATUS);
tmp |= PCI_STATUS_66MHZ;
__raw_writew(tmp, hose->reg_base + PCI_STATUS);
/* Done */
tmp = __raw_readl(hose->reg_base + SH4_PCICR);
tmp |= SH4_PCICR_PREFIX | SH4_PCICR_CFIN;
__raw_writel(tmp, hose->reg_base + SH4_PCICR);
}
static int __init sh7780_pci_init(void)
{
struct pci_channel *chan = &sh7780_pci_controller;
phys_addr_t memphys;
size_t memsize;
unsigned int id;
const char *type = NULL;
int ret;
u32 word;
const char *type;
int ret, i;
printk(KERN_NOTICE "PCI: Starting intialization.\n");
@ -65,17 +253,28 @@ static int __init sh7780_pci_init(void)
/* Enable CPU access to the PCIC registers. */
__raw_writel(PCIECR_ENBL, PCIECR);
id = __raw_readw(chan->reg_base + SH7780_PCIVID);
if (id != SH7780_VENDOR_ID) {
/* Reset */
__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST,
chan->reg_base + SH4_PCICR);
/*
* Wait for it to come back up. The spec says to allow for up to
* 1 second after toggling the reset pin, but in practice 100ms
* is more than enough.
*/
mdelay(100);
id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
if (id != PCI_VENDOR_ID_RENESAS) {
printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
return -ENODEV;
}
id = __raw_readw(chan->reg_base + SH7780_PCIDID);
type = (id == SH7763_DEVICE_ID) ? "SH7763" :
(id == SH7780_DEVICE_ID) ? "SH7780" :
(id == SH7781_DEVICE_ID) ? "SH7781" :
(id == SH7785_DEVICE_ID) ? "SH7785" :
id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
(id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
(id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
(id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
NULL;
if (unlikely(!type)) {
printk(KERN_ERR "PCI: Found an unsupported Renesas host "
@ -85,62 +284,119 @@ static int __init sh7780_pci_init(void)
printk(KERN_NOTICE "PCI: Found a Renesas %s host "
"controller, revision %d.\n", type,
__raw_readb(chan->reg_base + SH7780_PCIRID));
__raw_readb(chan->reg_base + PCI_REVISION_ID));
if ((ret = sh4_pci_check_direct(chan)) != 0)
/*
* Now throw it in to register initialization mode and
* start the real work.
*/
__raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR);
memphys = __pa(memory_start);
memsize = roundup_pow_of_two(memory_end - memory_start);
/*
* If there's more than 512MB of memory, we need to roll over to
* LAR1/LSR1.
*/
if (memsize > SZ_512M) {
__raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
__raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
chan->reg_base + SH4_PCILSR1);
memsize = SZ_512M;
} else {
/*
* Otherwise just zero it out and disable it.
*/
__raw_writel(0, chan->reg_base + SH4_PCILAR1);
__raw_writel(0, chan->reg_base + SH4_PCILSR1);
}
/*
* LAR0/LSR0 covers up to the first 512MB, which is enough to
* cover all of lowmem on most platforms.
*/
__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
__raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
chan->reg_base + SH4_PCILSR0);
/*
* Hook up the ERR and SERR IRQs.
*/
ret = sh7780_pci_setup_irqs(chan);
if (unlikely(ret))
return ret;
/*
* Set the class and sub-class codes.
* Disable the cache snoop controller for non-coherent DMA.
*/
__raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
chan->reg_base + SH7780_PCIBCC);
__raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
chan->reg_base + SH7780_PCISUB);
__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
/*
* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Setup the memory BARs
*/
pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
/* Set the values on window 0 PCI config registers */
pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
for (i = 1; i < chan->nr_resources; i++) {
struct resource *res = chan->resources + i;
resource_size_t size;
pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
if (unlikely(res->flags & IORESOURCE_IO))
continue;
/* Set up standard PCI config registers */
__raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
__raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
__raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
__raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
/*
* Make sure we're in the right physical addressing mode
* for dealing with the resource.
*/
if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) {
chan->nr_resources--;
continue;
}
__raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
size = resource_size(res);
/* Apply any last-minute PCIC fixups */
pci_fixup_pcic(chan);
/*
* The MBMR mask is calculated in units of 256kB, which
* keeps things pretty simple.
*/
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
chan->reg_base + SH7780_PCIMBMR(i - 1));
__raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
}
pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
/*
* And I/O.
*/
__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
#ifdef CONFIG_32BIT
pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
#endif
__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
/* Set IOBR for windows containing area specified in pci.h */
pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
SH7780_PCIIOBR);
pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
SH7780_PCIIOBMR);
/*
* Initialization mode complete, release the control register and
* enable round robin mode to stop device overruns/starvation.
*/
__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO,
chan->reg_base + SH4_PCICR);
/* SH7780 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */
word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
pci_write_reg(chan, word, SH4_PCICR);
ret = register_pci_controller(chan);
if (unlikely(ret))
goto err;
register_pci_controller(chan);
sh7780_pci66_init(chan);
printk(KERN_NOTICE "PCI: Running at %dMHz.\n",
(__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?
66 : 33);
return 0;
err:
sh7780_pci_teardown_irqs(chan);
return ret;
}
arch_initcall(sh7780_pci_init);

64
arch/sh/drivers/pci/pci-sh7780.h
View File

@ -12,12 +12,11 @@
#ifndef _PCI_SH7780_H_
#define _PCI_SH7780_H_
/* Platform Specific Values */
#define SH7780_VENDOR_ID 0x1912
#define SH7781_DEVICE_ID 0x0001
#define SH7780_DEVICE_ID 0x0002
#define SH7763_DEVICE_ID 0x0004
#define SH7785_DEVICE_ID 0x0007
#define PCI_VENDOR_ID_RENESAS 0x1912
#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
/* SH7780 Control Registers */
#define PCIECR 0xFE000008
@ -27,44 +26,9 @@
#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
/* SH7780 PCI Config Registers */
#define SH7780_PCIVID 0x000 /* Vendor ID */
#define SH7780_PCIDID 0x002 /* Device ID */
#define SH7780_PCICMD 0x004 /* Command */
#define SH7780_PCISTATUS 0x006 /* Status */
#define SH7780_PCIRID 0x008 /* Revision ID */
#define SH7780_PCIPIF 0x009 /* Program Interface */
#define SH7780_PCISUB 0x00a /* Sub class code */
#define SH7780_PCIBCC 0x00b /* Base class code */
#define SH7780_PCICLS 0x00c /* Cache line size */
#define SH7780_PCILTM 0x00d /* latency timer */
#define SH7780_PCIHDR 0x00e /* Header type */
#define SH7780_PCIBIST 0x00f /* BIST */
#define SH7780_PCIIBAR 0x010 /* IO Base address */
#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
#define SH7780_PCISID 0x02e /* Sub system ID */
#define SH7780_PCICP 0x034
#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
#define SH7780_PCICID 0x040
#define SH7780_PCINIP 0x041
#define SH7780_PCIPMC 0x042
#define SH7780_PCIPMCSR 0x044
#define SH7780_PCIPMCSR_BSE 0x046
#define SH7780_PCICDD 0x047
#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
#define SH7780_PCIAIR 0x11C /* Error Address Register */
@ -76,10 +40,8 @@
#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
#define SH7780_PCIMBR0 0x1E0
#define SH7780_PCIMBMR0 0x1E4
#define SH7780_PCIMBR2 0x1F0
#define SH7780_PCIMBMR2 0x1F4
#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))
#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))
#define SH7780_PCIIOBR 0x1F8
#define SH7780_PCIIOBMR 0x1FC
#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
@ -87,16 +49,4 @@
#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
/* General Memory Config Addresses */
#define SH7780_CS0_BASE_ADDR 0x0
#define SH7780_MEM_REGION_SIZE 0x04000000
#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
#endif /* _PCI_SH7780_H_ */

167
arch/sh/drivers/pci/pci.c
View File

@ -33,15 +33,22 @@ static int pci_initialized;
static void __devinit pcibios_scanbus(struct pci_channel *hose)
{
static int next_busno;
static int need_domain_info;
struct pci_bus *bus;
bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
hose->bus = bus;
need_domain_info = need_domain_info || hose->index;
hose->need_domain_info = need_domain_info;
if (bus) {
next_busno = bus->subordinate + 1;
/* Don't allow 8-bit bus number overflow inside the hose -
reserve some space for bridges. */
if (next_busno > 224)
if (next_busno > 224) {
next_busno = 0;
need_domain_info = 1;
}
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
@ -51,10 +58,21 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
static DEFINE_MUTEX(pci_scan_mutex);
void __devinit register_pci_controller(struct pci_channel *hose)
int __devinit register_pci_controller(struct pci_channel *hose)
{
request_resource(&iomem_resource, hose->mem_resource);
request_resource(&ioport_resource, hose->io_resource);
int i;
for (i = 0; i < hose->nr_resources; i++) {
struct resource *res = hose->resources + i;
if (res->flags & IORESOURCE_IO) {
if (request_resource(&ioport_resource, res) < 0)
goto out;
} else {
if (request_resource(&iomem_resource, res) < 0)
goto out;
}
}
*hose_tail = hose;
hose_tail = &hose->next;
@ -67,6 +85,11 @@ void __devinit register_pci_controller(struct pci_channel *hose)
"registering PCI controller with io_map_base unset\n");
}
/*
* Setup the ERR/PERR and SERR timers, if available.
*/
pcibios_enable_timers(hose);
/*
* Scan the bus if it is register after the PCI subsystem
* initialization.
@ -76,6 +99,15 @@ void __devinit register_pci_controller(struct pci_channel *hose)
pcibios_scanbus(hose);
mutex_unlock(&pci_scan_mutex);
}
return 0;
out:
for (--i; i >= 0; i--)
release_resource(&hose->resources[i]);
printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
return -1;
}
static int __init pcibios_init(void)
@ -127,11 +159,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev = bus->self;
struct list_head *ln;
struct pci_channel *chan = bus->sysdata;
struct pci_channel *hose = bus->sysdata;
if (!dev) {
bus->resource[0] = chan->io_resource;
bus->resource[1] = chan->mem_resource;
int i;
for (i = 0; i < hose->nr_resources; i++)
bus->resource[i] = hose->resources + i;
}
for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
@ -152,30 +186,25 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
{
struct pci_dev *dev = data;
struct pci_channel *chan = dev->sysdata;
struct pci_channel *hose = dev->sysdata;
resource_size_t start = res->start;
if (res->flags & IORESOURCE_IO) {
if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
start = PCIBIOS_MIN_IO + chan->io_resource->start;
if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
start = PCIBIOS_MIN_IO + hose->resources[0].start;
/*
* Put everything into 0x00-0xff region modulo 0x400.
*/
if (start & 0x300) {
if (start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
res->start = start;
}
} else if (res->flags & IORESOURCE_MEM) {
if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
}
return start;
}
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
struct resource *res)
{
struct pci_channel *hose = dev->sysdata;
unsigned long offset = 0;
@ -189,9 +218,8 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
region->end = res->end - offset;
}
void __devinit
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
{
struct pci_channel *hose = dev->sysdata;
unsigned long offset = 0;
@ -274,6 +302,86 @@ char * __devinit pcibios_setup(char *str)
return str;
}
static void __init
pcibios_bus_report_status_early(struct pci_channel *hose,
int top_bus, int current_bus,
unsigned int status_mask, int warn)
{
unsigned int pci_devfn;
u16 status;
int ret;
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn))
continue;
ret = early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_STATUS, &status);
if (ret != PCIBIOS_SUCCESSFUL)
continue;
if (status == 0xffff)
continue;
early_write_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_STATUS,
status & status_mask);
if (warn)
printk("(%02x:%02x: %04X) ", current_bus,
pci_devfn, status);
}
}
/*
* We can't use pci_find_device() here since we are
* called from interrupt context.
*/
static void __init_refok
pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
int warn)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
u16 status;
/*
* ignore host bridge - we handle
* that separately
*/
if (dev->bus->number == 0 && dev->devfn == 0)
continue;
pci_read_config_word(dev, PCI_STATUS, &status);
if (status == 0xffff)
continue;
if ((status & status_mask) == 0)
continue;
/* clear the status errors */
pci_write_config_word(dev, PCI_STATUS, status & status_mask);
if (warn)
printk("(%s: %04X) ", pci_name(dev), status);
}
list_for_each_entry(dev, &bus->devices, bus_list)
if (dev->subordinate)
pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}
void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
{
struct pci_channel *hose;
for (hose = hose_head; hose; hose = hose->next) {
if (unlikely(!hose->bus))
pcibios_bus_report_status_early(hose, hose_head->index,
hose->index, status_mask, warn);
else
pcibios_bus_report_status(hose->bus, status_mask, warn);
}
}
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine)
{
@ -302,9 +410,15 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
{
struct pci_channel *chan = dev->sysdata;
if (!chan->io_map_base)
if (unlikely(!chan->io_map_base)) {
chan->io_map_base = generic_io_base;
if (pci_domains_supported)
panic("To avoid data corruption io_map_base MUST be "
"set with multiple PCI domains.");
}
return (void __iomem *)(chan->io_map_base + port);
}
@ -321,20 +435,9 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
if (flags & IORESOURCE_IO)
return ioport_map_pci(dev, start, len);
/*
* Presently the IORESOURCE_MEM case is a bit special, most
* SH7751 style PCI controllers have PCI memory at a fixed
* location in the address space where no remapping is desired.
* With the IORESOURCE_MEM case more care has to be taken
* to inhibit page table mapping for legacy cores, but this is
* punted off to __ioremap().
* -- PFM.
*/
if (flags & IORESOURCE_MEM) {
if (flags & IORESOURCE_CACHEABLE)
return ioremap(start, len);
return ioremap_nocache(start, len);
}

207
arch/sh/drivers/pci/pcie-sh7786.c
View File

@ -1,7 +1,7 @@
/*
* Low-Level PCI Express Support for the SH7786
*
* Copyright (C) 2009 Paul Mundt
* Copyright (C) 2009 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
int (*port_init_hw)(struct sh7786_pcie_port *port);
} *sh7786_pcie_hwops;
static struct resource sh7786_pci_32bit_mem_resources[] = {
static struct resource sh7786_pci0_resources[] = {
{
.name = "pci0_mem",
.start = SH4A_PCIMEM_BASEA,
.end = SH4A_PCIMEM_BASEA + SZ_64M - 1,
.name = "PCIe0 IO",
.start = 0xfd000000,
.end = 0xfd000000 + SZ_8M - 1,
.flags = IORESOURCE_IO,
}, {
.name = "PCIe0 MEM 0",
.start = 0xc0000000,
.end = 0xc0000000 + SZ_512M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
.name = "PCIe0 MEM 1",
.start = 0x10000000,
.end = 0x10000000 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "pci1_mem",
.start = SH4A_PCIMEM_BASEA1,
.end = SH4A_PCIMEM_BASEA1 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "pci2_mem",
.start = SH4A_PCIMEM_BASEA2,
.end = SH4A_PCIMEM_BASEA2 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
.name = "PCIe0 MEM 2",
.start = 0xfe100000,
.end = 0xfe100000 + SZ_1M - 1,
},
};
static struct resource sh7786_pci_29bit_mem_resource = {
.start = SH4A_PCIMEM_BASE,
.end = SH4A_PCIMEM_BASE + SZ_64M - 1,
.flags = IORESOURCE_MEM,
static struct resource sh7786_pci1_resources[] = {
{
.name = "PCIe1 IO",
.start = 0xfd800000,
.end = 0xfd800000 + SZ_8M - 1,
.flags = IORESOURCE_IO,
}, {
.name = "PCIe1 MEM 0",
.start = 0xa0000000,
.end = 0xa0000000 + SZ_512M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
.name = "PCIe1 MEM 1",
.start = 0x30000000,
.end = 0x30000000 + SZ_256M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
.name = "PCIe1 MEM 2",
.start = 0xfe300000,
.end = 0xfe300000 + SZ_1M - 1,
},
};
static struct resource sh7786_pci_io_resources[] = {
static struct resource sh7786_pci2_resources[] = {
{
.name = "pci0_io",
.start = SH4A_PCIIO_BASE,
.end = SH4A_PCIIO_BASE + SZ_8M - 1,
.flags = IORESOURCE_IO,
.name = "PCIe2 IO",
.start = 0xfc800000,
.end = 0xfc800000 + SZ_4M - 1,
}, {
.name = "pci1_io",
.start = SH4A_PCIIO_BASE1,
.end = SH4A_PCIIO_BASE1 + SZ_8M - 1,
.flags = IORESOURCE_IO,
.name = "PCIe2 MEM 0",
.start = 0x80000000,
.end = 0x80000000 + SZ_512M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
.name = "pci2_io",
.start = SH4A_PCIIO_BASE2,
.end = SH4A_PCIIO_BASE2 + SZ_4M - 1,
.flags = IORESOURCE_IO,
.name = "PCIe2 MEM 1",
.start = 0x20000000,
.end = 0x20000000 + SZ_256M - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
.name = "PCIe2 MEM 2",
.start = 0xfcd00000,
.end = 0xfcd00000 + SZ_1M - 1,
},
};
extern struct pci_ops sh7786_pci_ops;
#define DEFINE_CONTROLLER(start, idx) \
{ \
.pci_ops = &sh7786_pci_ops, \
.reg_base = start, \
/* mem_resource filled in at probe time */ \
.mem_offset = 0, \
.io_resource = &sh7786_pci_io_resources[idx], \
.io_offset = 0, \
#define DEFINE_CONTROLLER(start, idx) \
{ \
.pci_ops = &sh7786_pci_ops, \
.resources = sh7786_pci##idx##_resources, \
.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
.reg_base = start, \
.mem_offset = 0, \
.io_offset = 0, \
}
static struct pci_channel sh7786_pci_channels[] = {
@ -180,7 +204,9 @@ static int pcie_init(struct sh7786_pcie_port *port)
{
struct pci_channel *chan = port->hose;
unsigned int data;
int ret;
phys_addr_t memphys;
size_t memsize;
int ret, i;
/* Begin initialization */
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
@ -203,15 +229,24 @@ static int pcie_init(struct sh7786_pcie_port *port)
data |= PCI_CAP_ID_EXP;
pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
/* Enable x4 link width and extended sync. */
/* Enable data link layer active state reporting */
pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
/* Enable extended sync and ASPM L0s support */
data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
data &= ~(PCI_EXP_LNKSTA_NLW << 16);
data |= (1 << 22) | PCI_EXP_LNKCTL_ES;
data &= ~PCI_EXP_LNKCTL_ASPMC;
data |= PCI_EXP_LNKCTL_ES | 1;
pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
/* Write out the physical slot number */
data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
data &= ~PCI_EXP_SLTCAP_PSN;
data |= (port->index + 1) << 19;
pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
/* Set the completion timer timeout to the maximum 32ms. */
data = pci_read_reg(chan, SH4A_PCIETLCTLR);
data &= ~0xffff;
data &= ~0x3f00;
data |= 0x32 << 8;
pci_write_reg(chan, data, SH4A_PCIETLCTLR);
@ -224,6 +259,33 @@ static int pcie_init(struct sh7786_pcie_port *port)
data |= (0xff << 16);
pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
memphys = __pa(memory_start);
memsize = roundup_pow_of_two(memory_end - memory_start);
/*
* If there's more than 512MB of memory, we need to roll over to
* LAR1/LAMR1.
*/
if (memsize > SZ_512M) {
__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
chan->reg_base + SH4A_PCIELAMR1);
memsize = SZ_512M;
} else {
/*
* Otherwise just zero it out and disable it.
*/
__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
}
/*
* LAR0/LAMR0 covers up to the first 512MB, which is enough to
* cover all of lowmem on most platforms.
*/
__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
/* Finish initialization */
data = pci_read_reg(chan, SH4A_PCIETCTLR);
data |= 0x1;
@ -243,10 +305,14 @@ static int pcie_init(struct sh7786_pcie_port *port)
if (unlikely(ret != 0))
return -ENODEV;
pci_write_reg(chan, 0x00100007, SH4A_PCIEPCICONF1);
data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
(PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
pci_write_reg(chan, 0x000050A0, SH4A_PCIEEXPCAP2);
wmb();
@ -254,15 +320,32 @@ static int pcie_init(struct sh7786_pcie_port *port)
printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
port->index, (data >> 20) & 0x3f);
pci_write_reg(chan, 0x007c0000, SH4A_PCIEPAMR0);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH0);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL0);
pci_write_reg(chan, 0x80000100, SH4A_PCIEPTCTLR0);
pci_write_reg(chan, 0x03fc0000, SH4A_PCIEPAMR2);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH2);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL2);
pci_write_reg(chan, 0x80000000, SH4A_PCIEPTCTLR2);
for (i = 0; i < chan->nr_resources; i++) {
struct resource *res = chan->resources + i;
resource_size_t size;
u32 enable_mask;
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
size = resource_size(res);
/*
* The PAMR mask is calculated in units of 256kB, which
* keeps things pretty simple.
*/
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
chan->reg_base + SH4A_PCIEPAMR(i));
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
enable_mask = MASK_PARE;
if (res->flags & IORESOURCE_IO)
enable_mask |= MASK_SPC;
pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
}
return 0;
}
@ -296,9 +379,7 @@ static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
if (unlikely(ret < 0))
return ret;
register_pci_controller(port->hose);
return 0;
return register_pci_controller(port->hose);
}
static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
@ -332,17 +413,7 @@ static int __init sh7786_pcie_init(void)
port->index = i;
port->hose = sh7786_pci_channels + i;
port->hose->io_map_base = port->hose->io_resource->start;
/*
* Check if we are booting in 29 or 32-bit mode
*
* 32-bit mode provides each controller with its own
* memory window, while 29-bit mode uses a shared one.
*/
port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
&sh7786_pci_32bit_mem_resources[i] :
&sh7786_pci_29bit_mem_resource;
port->hose->io_map_base = port->hose->resources[0].start;
ret |= sh7786_pcie_hwops->port_init_hw(port);
}

74
arch/sh/drivers/pci/pcie-sh7786.h
View File

@ -30,47 +30,9 @@
* for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
*/
/* PCI0-0: PCI I/O space */
#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
/* PCI0-1: PCI memory space 29-bit address */
#define SH4A_PCIMEM_BASE 0x10000000
#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
/* PCI0-2: PCI memory space 32-bit address */
#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
#define SH4A_PCI_DEVICE_ID 0x0002
#define SH4A_PCI_VENDOR_ID 0x1912
// PCI compatible 000-03f
#define PCI_CMD 0x004
#define PCI_RID 0x008
#define PCI_IBAR 0x010
#define PCI_MBAR0 0x014
#define PCI_MBAR1 0x018
/* PCI power management/MSI/capablity 040-0ff */
/* PCIE extended 100-fff */
/* SH7786 device identification */ // Rev1.171
#define SH4A_PVR (0xFF000030)
#define SH4A_PVR_SHX3 (0x10400000)
#define SH4A_PRR (0xFF000044)
#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
/* SPVCR0 */
#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
#define BITS_TOP_MB (24)
@ -350,23 +312,23 @@
#define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
/* PCIEPARL0 */
#define SH4A_PCIEPARL0 (0x020400) /* R/W R/W 0x0000 0000 32 */
/* PCIEPARL */
#define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAL (18)
#define MASK_PAL (0x3fff<<BITS_PAL)
/* PCIEPARH0 */
#define SH4A_PCIEPARH0 (0x020404) /* R/W R/W 0x0000 0000 32 */
/* PCIEPARH */
#define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAH (0)
#define MASK_PAH (0xffffffff<<BITS_PAH)
/* PCIEPAMR0 */
#define SH4A_PCIEPAMR0 (0x020408) /* R/W R/W 0x0000 0000 32 */
/* PCIEPAMR */
#define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAM (18)
#define MASK_PAM (0x3fff<<BITS_PAM)
/* PCIEPTCTLR0 */
#define SH4A_PCIEPTCTLR0 (0x02040C) /* R/W R/W 0x0000 0000 32 */
/* PCIEPTCTLR */
#define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20))
#define BITS_PARE (31)
#define MASK_PARE (0x1<<BITS_PARE)
#define BITS_TC (20)
@ -378,26 +340,6 @@
#define BITS_SPC (8)
#define MASK_SPC (0x1<<BITS_SPC)
#define SH4A_PCIEPARL1 (0x020420) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARH1 (0x020424) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPAMR1 (0x020428) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPTCTLR1 (0x02042C) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARL2 (0x020440) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARH2 (0x020444) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPAMR2 (0x020448) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPTCTLR2 (0x02044C) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARL3 (0x020460) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARH3 (0x020464) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPAMR3 (0x020468) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPTCTLR3 (0x02046C) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARL4 (0x020480) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARH4 (0x020484) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPAMR4 (0x020488) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPTCTLR4 (0x02048C) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARL5 (0x0204A0) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPARH5 (0x0204A4) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPAMR5 (0x0204A8) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPTCTLR5 (0x0204AC) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */

8
arch/sh/drivers/superhyway/ops-sh4-202.c
View File

@ -134,8 +134,8 @@ static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
*
* Do not trust the documentation, for it is evil.
*/
vcrh = ctrl_inl(base);
vcrl = ctrl_inl(base + sizeof(u32));
vcrh = __raw_readl(base);
vcrl = __raw_readl(base + sizeof(u32));
tmp = ((u64)vcrh << 32) | vcrl;
memcpy(vcr, &tmp, sizeof(u64));
@ -147,8 +147,8 @@ static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
{
u64 tmp = *(u64 *)&vcr;
ctrl_outl((tmp >> 32) & 0xffffffff, base);
ctrl_outl(tmp & 0xffffffff, base + sizeof(u32));
__raw_writel((tmp >> 32) & 0xffffffff, base);
__raw_writel(tmp & 0xffffffff, base + sizeof(u32));
return 0;
}

4
arch/sh/include/asm/Kbuild
View File

@ -1,6 +1,8 @@
include include/asm-generic/Kbuild.asm
header-y += cachectl.h cpu-features.h
header-y += cachectl.h
header-y += cpu-features.h
header-y += hw_breakpoint.h
unifdef-y += unistd_32.h
unifdef-y += unistd_64.h

18
arch/sh/include/asm/addrspace.h
View File

@ -28,7 +28,7 @@
/* Returns the privileged segment base of a given address */
#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
#ifdef CONFIG_29BIT
/*
* Map an address to a certain privileged segment
*/
@ -40,7 +40,15 @@
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
#define P4SEGADDR(a) \
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
#endif /* 29BIT || PMB_FIXED */
#else
/*
* These will never work in 32-bit, don't even bother.
*/
#define P1SEGADDR(a) __futile_remapping_attempt
#define P2SEGADDR(a) __futile_remapping_attempt
#define P3SEGADDR(a) __futile_remapping_attempt
#define P4SEGADDR(a) __futile_remapping_attempt
#endif
#endif /* P1SEG */
/* Check if an address can be reached in 29 bits */
@ -57,11 +65,5 @@
#define P3_ADDR_MAX P4SEG
#endif
#ifndef __ASSEMBLY__
#ifdef CONFIG_PMB
extern int __in_29bit_mode(void);
#endif /* CONFIG_PMB */
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_ADDRSPACE_H */

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