ARM i.MX53: Some bug fix about MX53 MSL code
1. pll_base address should return right value 2. uart parent clk is from pll3 Signed-off-by: Yong Shen <yong.shen@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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96de6d447f
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644b1d586d
2 changed files with 28 additions and 1 deletions
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@ -127,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0,
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return -EINVAL;
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return -EINVAL;
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}
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}
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static inline void __iomem *_get_pll_base(struct clk *pll)
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static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
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{
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{
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if (pll == &pll1_main_clk)
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if (pll == &pll1_main_clk)
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return MX51_DPLL1_BASE;
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return MX51_DPLL1_BASE;
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@ -135,6 +135,20 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
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return MX51_DPLL2_BASE;
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return MX51_DPLL2_BASE;
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else if (pll == &pll3_sw_clk)
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else if (pll == &pll3_sw_clk)
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return MX51_DPLL3_BASE;
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return MX51_DPLL3_BASE;
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else
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BUG();
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return NULL;
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}
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static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
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{
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if (pll == &pll1_main_clk)
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return MX53_DPLL1_BASE;
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else if (pll == &pll2_sw_clk)
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return MX53_DPLL2_BASE;
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else if (pll == &pll3_sw_clk)
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return MX53_DPLL3_BASE;
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else if (pll == &mx53_pll4_sw_clk)
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else if (pll == &mx53_pll4_sw_clk)
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return MX53_DPLL4_BASE;
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return MX53_DPLL4_BASE;
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else
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else
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@ -143,6 +157,14 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
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return NULL;
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return NULL;
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}
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}
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static inline void __iomem *_get_pll_base(struct clk *pll)
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{
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if (cpu_is_mx51())
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return _mx51_get_pll_base(pll);
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else
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return _mx53_get_pll_base(pll);
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}
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static unsigned long clk_pll_get_rate(struct clk *clk)
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static unsigned long clk_pll_get_rate(struct clk *clk)
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{
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{
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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@ -1341,6 +1363,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
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clk_tree_init();
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clk_tree_init();
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clk_set_parent(&uart_root_clk, &pll3_sw_clk);
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clk_enable(&cpu_clk);
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clk_enable(&cpu_clk);
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clk_enable(&main_bus_clk);
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clk_enable(&main_bus_clk);
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@ -19,6 +19,10 @@
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#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
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#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
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/*MX53*/
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/*MX53*/
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#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
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#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
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#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
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#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
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#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
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#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
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/* PLL Register Offsets */
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/* PLL Register Offsets */
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