MIPS: Alchemy: Extended DB1200 board support.
Create own directory for DB1200 code and update it with new features. - SPI support: - tmp121 temperature sensor - SPI flash on DB1200 - I2C support - NE1619 sensor - AT24 eeprom - I2C/SPI can be selected at boot time via switch S6.8 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
206aa6cdad
commit
63323ec54a
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@ -164,9 +164,6 @@ void au1000_halt(void)
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#ifdef CONFIG_MIPS_MIRAGE
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gpio_direction_output(210, 1);
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#endif
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#ifdef CONFIG_MIPS_DB1200
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au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
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#endif
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#ifdef CONFIG_PM
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au_sleep();
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@ -11,7 +11,7 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/
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obj-$(CONFIG_MIPS_PB1550) += pb1550/
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obj-$(CONFIG_MIPS_DB1000) += db1x00/
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obj-$(CONFIG_MIPS_DB1100) += db1x00/
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obj-$(CONFIG_MIPS_DB1200) += pb1200/
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obj-$(CONFIG_MIPS_DB1200) += db1200/
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obj-$(CONFIG_MIPS_DB1500) += db1x00/
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obj-$(CONFIG_MIPS_DB1550) += db1x00/
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obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
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@ -0,0 +1 @@
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obj-y += setup.o platform.o
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@ -0,0 +1,510 @@
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/*
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* DBAu1200 board platform device registration
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*
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* Copyright (C) 2008-2009 Manuel Lauss
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/leds.h>
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#include <linux/mmc/host.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/smc91x.h>
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#include <asm/mach-au1x00/au1100_mmc.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1550_spi.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <asm/mach-db1x00/db1200.h>
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#include "../platform.h"
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static struct mtd_partition db1200_spiflash_parts[] = {
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{
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.name = "DB1200 SPI flash",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct flash_platform_data db1200_spiflash_data = {
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.name = "s25fl001",
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.parts = db1200_spiflash_parts,
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.nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
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.type = "m25p10",
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};
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static struct spi_board_info db1200_spi_devs[] __initdata = {
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{
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/* TI TMP121AIDBVR temp sensor */
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.modalias = "tmp121",
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.max_speed_hz = 2000000,
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.bus_num = 0,
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.chip_select = 0,
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.mode = 0,
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},
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{
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/* Spansion S25FL001D0FMA SPI flash */
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.modalias = "m25p80",
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.max_speed_hz = 50000000,
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.bus_num = 0,
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.chip_select = 1,
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.mode = 0,
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.platform_data = &db1200_spiflash_data,
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},
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};
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static struct i2c_board_info db1200_i2c_devs[] __initdata = {
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{
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/* AT24C04-10 I2C eeprom */
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I2C_BOARD_INFO("24c04", 0x52),
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},
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{
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/* Philips NE1619 temp/voltage sensor (adm1025 drv) */
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I2C_BOARD_INFO("ne1619", 0x2d),
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},
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{
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/* I2S audio codec WM8731 */
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I2C_BOARD_INFO("wm8731", 0x1b),
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},
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};
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/**********************************************************************/
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static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
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ioaddr &= 0xffffff00;
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if (ctrl & NAND_CLE) {
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ioaddr += MEM_STNAND_CMD;
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} else if (ctrl & NAND_ALE) {
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ioaddr += MEM_STNAND_ADDR;
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} else {
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/* assume we want to r/w real data by default */
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ioaddr += MEM_STNAND_DATA;
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}
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this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
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if (cmd != NAND_CMD_NONE) {
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__raw_writeb(cmd, this->IO_ADDR_W);
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wmb();
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}
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}
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static int au1200_nand_device_ready(struct mtd_info *mtd)
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{
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return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
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}
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static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
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static struct mtd_partition db1200_nand_parts[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024,
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},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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},
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};
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struct platform_nand_data db1200_nand_platdata = {
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.chip = {
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.nr_chips = 1,
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.chip_offset = 0,
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.nr_partitions = ARRAY_SIZE(db1200_nand_parts),
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.partitions = db1200_nand_parts,
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.chip_delay = 20,
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.part_probe_types = db1200_part_probes,
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},
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.ctrl = {
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.dev_ready = au1200_nand_device_ready,
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.cmd_ctrl = au1200_nand_cmd_ctrl,
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},
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};
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static struct resource db1200_nand_res[] = {
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[0] = {
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.start = DB1200_NAND_PHYS_ADDR,
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.end = DB1200_NAND_PHYS_ADDR + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device db1200_nand_dev = {
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.name = "gen_nand",
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.num_resources = ARRAY_SIZE(db1200_nand_res),
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.resource = db1200_nand_res,
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.id = -1,
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.dev = {
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.platform_data = &db1200_nand_platdata,
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}
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};
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/**********************************************************************/
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static struct smc91x_platdata db1200_eth_data = {
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.flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
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.leda = RPC_LED_100_10,
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.ledb = RPC_LED_TX_RX,
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};
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static struct resource db1200_eth_res[] = {
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[0] = {
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.start = DB1200_ETH_PHYS_ADDR,
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.end = DB1200_ETH_PHYS_ADDR + 0xf,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DB1200_ETH_INT,
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.end = DB1200_ETH_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device db1200_eth_dev = {
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.dev = {
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.platform_data = &db1200_eth_data,
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},
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.name = "smc91x",
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.id = -1,
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.num_resources = ARRAY_SIZE(db1200_eth_res),
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.resource = db1200_eth_res,
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};
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/**********************************************************************/
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static struct resource db1200_ide_res[] = {
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[0] = {
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.start = DB1200_IDE_PHYS_ADDR,
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.end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DB1200_IDE_INT,
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.end = DB1200_IDE_INT,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 ide_dmamask = DMA_32BIT_MASK;
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static struct platform_device db1200_ide_dev = {
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.name = "au1200-ide",
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.id = 0,
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.dev = {
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.dma_mask = &ide_dmamask,
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.coherent_dma_mask = DMA_32BIT_MASK,
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},
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.num_resources = ARRAY_SIZE(db1200_ide_res),
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.resource = db1200_ide_res,
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};
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/**********************************************************************/
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static struct platform_device db1200_rtc_dev = {
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.name = "rtc-au1xxx",
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.id = -1,
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};
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/**********************************************************************/
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/* SD carddetects: they're supposed to be edge-triggered, but ack
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* doesn't seem to work (CPLD Rev 2). Instead, the screaming one
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* is disabled and its counterpart enabled. The 500ms timeout is
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* because the carddetect isn't debounced in hardware.
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*/
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static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
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{
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void(*mmc_cd)(struct mmc_host *, unsigned long);
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if (irq == DB1200_SD0_INSERT_INT) {
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disable_irq_nosync(DB1200_SD0_INSERT_INT);
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enable_irq(DB1200_SD0_EJECT_INT);
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} else {
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disable_irq_nosync(DB1200_SD0_EJECT_INT);
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enable_irq(DB1200_SD0_INSERT_INT);
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}
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/* link against CONFIG_MMC=m */
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mmc_cd = symbol_get(mmc_detect_change);
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if (mmc_cd) {
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mmc_cd(ptr, msecs_to_jiffies(500));
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symbol_put(mmc_detect_change);
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}
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return IRQ_HANDLED;
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}
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static int db1200_mmc_cd_setup(void *mmc_host, int en)
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{
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int ret;
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if (en) {
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ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
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IRQF_DISABLED, "sd_insert", mmc_host);
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if (ret)
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goto out;
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ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
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IRQF_DISABLED, "sd_eject", mmc_host);
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if (ret) {
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free_irq(DB1200_SD0_INSERT_INT, mmc_host);
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goto out;
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}
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if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
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enable_irq(DB1200_SD0_EJECT_INT);
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else
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enable_irq(DB1200_SD0_INSERT_INT);
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} else {
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free_irq(DB1200_SD0_INSERT_INT, mmc_host);
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free_irq(DB1200_SD0_EJECT_INT, mmc_host);
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}
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ret = 0;
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out:
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return ret;
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}
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static void db1200_mmc_set_power(void *mmc_host, int state)
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{
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if (state) {
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bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
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msleep(400); /* stabilization time */
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} else
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bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
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}
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static int db1200_mmc_card_readonly(void *mmc_host)
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{
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return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
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}
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static int db1200_mmc_card_inserted(void *mmc_host)
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{
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return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
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}
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static void db1200_mmcled_set(struct led_classdev *led,
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enum led_brightness brightness)
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{
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if (brightness != LED_OFF)
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bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
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else
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bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
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}
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static struct led_classdev db1200_mmc_led = {
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.brightness_set = db1200_mmcled_set,
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};
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/* needed by arch/mips/alchemy/common/platform.c */
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struct au1xmmc_platform_data au1xmmc_platdata[] = {
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[0] = {
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.cd_setup = db1200_mmc_cd_setup,
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.set_power = db1200_mmc_set_power,
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.card_inserted = db1200_mmc_card_inserted,
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.card_readonly = db1200_mmc_card_readonly,
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.led = &db1200_mmc_led,
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},
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};
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/**********************************************************************/
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static struct resource au1200_psc0_res[] = {
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[0] = {
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.start = PSC0_PHYS_ADDR,
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.end = PSC0_PHYS_ADDR + 0x000fffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1200_PSC0_INT,
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.end = AU1200_PSC0_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = DSCR_CMD0_PSC0_TX,
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.end = DSCR_CMD0_PSC0_TX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = DSCR_CMD0_PSC0_RX,
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.end = DSCR_CMD0_PSC0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device db1200_i2c_dev = {
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.name = "au1xpsc_smbus",
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.id = 0, /* bus number */
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.num_resources = ARRAY_SIZE(au1200_psc0_res),
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.resource = au1200_psc0_res,
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};
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static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
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{
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if (cs)
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bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
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else
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bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
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}
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static struct au1550_spi_info db1200_spi_platdata = {
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.mainclk_hz = 50000000, /* PSC0 clock */
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.num_chipselect = 2,
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.activate_cs = db1200_spi_cs_en,
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};
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static u64 spi_dmamask = DMA_32BIT_MASK;
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static struct platform_device db1200_spi_dev = {
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.dev = {
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.dma_mask = &spi_dmamask,
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.coherent_dma_mask = DMA_32BIT_MASK,
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.platform_data = &db1200_spi_platdata,
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},
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.name = "au1550-spi",
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.id = 0, /* bus number */
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.num_resources = ARRAY_SIZE(au1200_psc0_res),
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.resource = au1200_psc0_res,
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};
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static struct platform_device *db1200_devs[] __initdata = {
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NULL, /* PSC0, selected by S6.8 */
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&db1200_ide_dev,
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&db1200_eth_dev,
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&db1200_rtc_dev,
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&db1200_nand_dev,
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};
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static int __init db1200_dev_init(void)
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{
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unsigned long pfc;
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unsigned short sw;
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int swapped;
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i2c_register_board_info(0, db1200_i2c_devs,
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ARRAY_SIZE(db1200_i2c_devs));
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spi_register_board_info(db1200_spi_devs,
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ARRAY_SIZE(db1200_i2c_devs));
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/* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
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*/
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/* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
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* this pin is claimed by PSC0 (unused though, but pinmux doesn't
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* allow to free it without crippling the SPI interface).
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* As a result, in SPI mode, OTG simply won't work (PSC0 uses
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* it as an input pin which is pulled high on the boards).
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*/
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pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
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||||
/* switch off OTG VBUS supply */
|
||||
gpio_request(215, "otg-vbus");
|
||||
gpio_direction_output(215, 1);
|
||||
|
||||
printk(KERN_INFO "DB1200 device configuration:\n");
|
||||
|
||||
sw = bcsr_read(BCSR_SWITCHES);
|
||||
if (sw & BCSR_SWITCHES_DIP_8) {
|
||||
db1200_devs[0] = &db1200_i2c_dev;
|
||||
bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
|
||||
|
||||
pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
|
||||
|
||||
printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
|
||||
printk(KERN_INFO " OTG port VBUS supply available!\n");
|
||||
} else {
|
||||
db1200_devs[0] = &db1200_spi_dev;
|
||||
bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
|
||||
|
||||
pfc |= (1 << 17); /* PSC0 owns GPIO215 */
|
||||
|
||||
printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
|
||||
printk(KERN_INFO " OTG port VBUS supply disabled\n");
|
||||
}
|
||||
__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
|
||||
wmb();
|
||||
|
||||
db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
|
||||
PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
|
||||
PCMCIA_MEM_PSEUDO_PHYS,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
|
||||
PCMCIA_IO_PSEUDO_PHYS,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
|
||||
DB1200_PC0_INT,
|
||||
DB1200_PC0_INSERT_INT,
|
||||
/*DB1200_PC0_STSCHG_INT*/0,
|
||||
DB1200_PC0_EJECT_INT,
|
||||
0);
|
||||
|
||||
db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1,
|
||||
DB1200_PC1_INT,
|
||||
DB1200_PC1_INSERT_INT,
|
||||
/*DB1200_PC1_STSCHG_INT*/0,
|
||||
DB1200_PC1_EJECT_INT,
|
||||
1);
|
||||
|
||||
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
|
||||
db1x_register_norflash(64 << 20, 2, swapped);
|
||||
|
||||
return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
|
||||
}
|
||||
device_initcall(db1200_dev_init);
|
||||
|
||||
/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
|
||||
int board_au1200fb_panel(void)
|
||||
{
|
||||
return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
|
||||
}
|
||||
|
||||
int board_au1200fb_panel_init(void)
|
||||
{
|
||||
/* Apply power */
|
||||
bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
|
||||
BCSR_BOARD_LCDBL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_au1200fb_panel_shutdown(void)
|
||||
{
|
||||
/* Remove power */
|
||||
bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
|
||||
BCSR_BOARD_LCDBL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Alchemy/AMD/RMI DB1200 board setup.
|
||||
*
|
||||
* Licensed under the terms outlined in the file COPYING in the root of
|
||||
* this source archive.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pm.h>
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-db1x00/bcsr.h>
|
||||
#include <asm/mach-db1x00/db1200.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Alchemy Db1200";
|
||||
}
|
||||
|
||||
static void board_power_off(void)
|
||||
{
|
||||
bcsr_write(BCSR_RESETS, 0);
|
||||
bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
|
||||
}
|
||||
|
||||
void board_reset(void)
|
||||
{
|
||||
bcsr_write(BCSR_RESETS, 0);
|
||||
bcsr_write(BCSR_SYSTEM, 0);
|
||||
}
|
||||
|
||||
void __init board_setup(void)
|
||||
{
|
||||
unsigned long freq0, clksrc, div, pfc;
|
||||
unsigned short whoami;
|
||||
|
||||
bcsr_init(DB1200_BCSR_PHYS_ADDR,
|
||||
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
|
||||
|
||||
whoami = bcsr_read(BCSR_WHOAMI);
|
||||
printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
|
||||
" Board-ID %d Daughtercard ID %d\n",
|
||||
(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
|
||||
|
||||
/* SMBus/SPI on PSC0, Audio on PSC1 */
|
||||
pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
|
||||
pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
|
||||
pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
|
||||
pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
|
||||
__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
|
||||
wmb();
|
||||
|
||||
/* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
|
||||
* CPU clock; all other clock generators off/unused.
|
||||
*/
|
||||
div = (get_au1x00_speed() + 25000000) / 50000000;
|
||||
if (div & 1)
|
||||
div++;
|
||||
div = ((div >> 1) - 1) & 0xff;
|
||||
|
||||
freq0 = div << SYS_FC_FRDIV0_BIT;
|
||||
__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
|
||||
wmb();
|
||||
freq0 |= SYS_FC_FE0; /* enable F0 */
|
||||
__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
|
||||
wmb();
|
||||
|
||||
/* psc0_intclk comes 1:1 from F0 */
|
||||
clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
|
||||
__raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
|
||||
wmb();
|
||||
|
||||
pm_power_off = board_power_off;
|
||||
_machine_halt = board_power_off;
|
||||
_machine_restart = (void(*)(char *))board_reset;
|
||||
}
|
||||
|
||||
/* use the hexleds to count the number of times the cpu has entered
|
||||
* wait, the dots to indicate whether the CPU is currently idle or
|
||||
* active (dots off = sleeping, dots on = working) for cases where
|
||||
* the number doesn't change for a long(er) period of time.
|
||||
*/
|
||||
static void db1200_wait(void)
|
||||
{
|
||||
__asm__(" .set push \n"
|
||||
" .set mips3 \n"
|
||||
" .set noreorder \n"
|
||||
" cache 0x14, 0(%0) \n"
|
||||
" cache 0x14, 32(%0) \n"
|
||||
" cache 0x14, 64(%0) \n"
|
||||
/* dots off: we're about to call wait */
|
||||
" lui $26, 0xb980 \n"
|
||||
" ori $27, $0, 3 \n"
|
||||
" sb $27, 0x18($26) \n"
|
||||
" sync \n"
|
||||
" nop \n"
|
||||
" wait \n"
|
||||
" nop \n"
|
||||
" nop \n"
|
||||
" nop \n"
|
||||
" nop \n"
|
||||
" nop \n"
|
||||
/* dots on: there's work to do, increment cntr */
|
||||
" lui $26, 0xb980 \n"
|
||||
" sb $0, 0x18($26) \n"
|
||||
" lui $26, 0xb9c0 \n"
|
||||
" lb $27, 0($26) \n"
|
||||
" addiu $27, $27, 1 \n"
|
||||
" sb $27, 0($26) \n"
|
||||
" sync \n"
|
||||
" .set pop \n"
|
||||
: : "r" (db1200_wait));
|
||||
}
|
||||
|
||||
static int __init db1200_arch_init(void)
|
||||
{
|
||||
/* GPIO7 is low-level triggered CPLD cascade */
|
||||
set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
|
||||
bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
|
||||
|
||||
/* do not autoenable these: CPLD has broken edge int handling,
|
||||
* and the CD handler setup requires manual enabling to work
|
||||
* around that.
|
||||
*/
|
||||
irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
|
||||
irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
|
||||
|
||||
if (cpu_wait)
|
||||
cpu_wait = db1200_wait;
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(db1200_arch_init);
|
||||
|
|
@ -58,16 +58,9 @@ void __init board_setup(void)
|
|||
{
|
||||
char *argptr;
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1200
|
||||
printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
|
||||
bcsr_init(PB1200_BCSR_PHYS_ADDR,
|
||||
PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
|
||||
#endif
|
||||
#ifdef CONFIG_MIPS_DB1200
|
||||
printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
|
||||
bcsr_init(DB1200_BCSR_PHYS_ADDR,
|
||||
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
|
||||
#endif
|
||||
|
||||
argptr = prom_getcmdline();
|
||||
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||||
|
|
@ -149,7 +142,6 @@ void __init board_setup(void)
|
|||
|
||||
static int __init pb1200_init_irq(void)
|
||||
{
|
||||
#ifdef CONFIG_MIPS_PB1200
|
||||
/* We have a problem with CPLD rev 3. */
|
||||
if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
|
||||
printk(KERN_ERR "WARNING!!!\n");
|
||||
|
|
@ -169,7 +161,6 @@ static int __init pb1200_init_irq(void)
|
|||
printk(KERN_ERR "WARNING!!!\n");
|
||||
panic("Game over. Your score is 0.");
|
||||
}
|
||||
#endif
|
||||
|
||||
set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
|
||||
bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
|
||||
|
|
|
|||
|
|
@ -68,7 +68,6 @@ static struct led_classdev pb1200mmc_led = {
|
|||
.brightness_set = pb1200_mmcled_set,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_MIPS_DB1200
|
||||
static void pb1200mmc1_set_power(void *mmc_host, int state)
|
||||
{
|
||||
if (state)
|
||||
|
|
@ -88,7 +87,6 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
|
|||
{
|
||||
return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
|
||||
[0] = {
|
||||
|
|
@ -98,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
|
|||
.cd_setup = NULL, /* use poll-timer in driver */
|
||||
.led = &pb1200mmc_led,
|
||||
},
|
||||
#ifndef CONFIG_MIPS_DB1200
|
||||
[1] = {
|
||||
.set_power = pb1200mmc1_set_power,
|
||||
.card_inserted = pb1200mmc1_card_inserted,
|
||||
|
|
@ -106,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
|
|||
.cd_setup = NULL, /* use poll-timer in driver */
|
||||
.led = &pb1200mmc_led,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource ide_resources[] = {
|
||||
|
|
@ -174,7 +170,6 @@ static int __init board_register_devices(void)
|
|||
{
|
||||
int swapped;
|
||||
|
||||
#ifdef CONFIG_MIPS_PB1200
|
||||
db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
|
||||
PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
|
||||
PCMCIA_MEM_PSEUDO_PHYS,
|
||||
|
|
@ -198,38 +193,9 @@ static int __init board_register_devices(void)
|
|||
/*PB1200_PC1_STSCHG_INT*/0,
|
||||
PB1200_PC1_EJECT_INT,
|
||||
1);
|
||||
#else
|
||||
db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
|
||||
PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
|
||||
PCMCIA_MEM_PSEUDO_PHYS,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
|
||||
PCMCIA_IO_PSEUDO_PHYS,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
|
||||
DB1200_PC0_INT,
|
||||
DB1200_PC0_INSERT_INT,
|
||||
/*DB1200_PC0_STSCHG_INT*/0,
|
||||
DB1200_PC0_EJECT_INT,
|
||||
0);
|
||||
|
||||
db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00400000,
|
||||
PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1,
|
||||
DB1200_PC1_INT,
|
||||
DB1200_PC1_INSERT_INT,
|
||||
/*DB1200_PC1_STSCHG_INT*/0,
|
||||
DB1200_PC1_EJECT_INT,
|
||||
1);
|
||||
#endif
|
||||
|
||||
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
|
||||
#ifdef CONFIG_MIPS_PB1200
|
||||
db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
|
||||
#else
|
||||
db1x_register_norflash(64 * 1024 * 1024, 2, swapped);
|
||||
#endif
|
||||
|
||||
return platform_add_devices(board_platform_devices,
|
||||
ARRAY_SIZE(board_platform_devices));
|
||||
|
|
|
|||
|
|
@ -28,24 +28,6 @@
|
|||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
|
||||
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
|
||||
/*
|
||||
* SPI and SMB are muxed on the DBAu1200 board.
|
||||
* Refer to board documentation.
|
||||
*/
|
||||
#define SPI_PSC_BASE PSC0_BASE_ADDR
|
||||
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
|
||||
/*
|
||||
* AC'97 and I2S are muxed on the DBAu1200 board.
|
||||
* Refer to board documentation.
|
||||
*/
|
||||
#define AC97_PSC_BASE PSC1_BASE_ADDR
|
||||
#define I2S_PSC_BASE PSC1_BASE_ADDR
|
||||
|
||||
/* Bit positions for the different interrupt sources */
|
||||
#define BCSR_INT_IDE 0x0001
|
||||
#define BCSR_INT_ETH 0x0002
|
||||
|
|
@ -62,17 +44,15 @@
|
|||
#define BCSR_INT_SD0INSERT 0x1000
|
||||
#define BCSR_INT_SD0EJECT 0x2000
|
||||
|
||||
#define SMC91C111_PHYS_ADDR 0x19000300
|
||||
#define SMC91C111_INT DB1200_ETH_INT
|
||||
|
||||
#define IDE_PHYS_ADDR 0x18800000
|
||||
#define IDE_REG_SHIFT 5
|
||||
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define IDE_INT DB1200_IDE_INT
|
||||
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
|
||||
#define IDE_RQSIZE 128
|
||||
|
||||
#define NAND_PHYS_ADDR 0x20000000
|
||||
#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
|
||||
#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define DB1200_ETH_PHYS_ADDR 0x19000300
|
||||
#define DB1200_NAND_PHYS_ADDR 0x20000000
|
||||
|
||||
/*
|
||||
* External Interrupts for DBAu1200 as of 8/6/2004.
|
||||
|
|
@ -82,7 +62,7 @@
|
|||
* Example: IDE bis pos is = 64 - 64
|
||||
* ETH bit pos is = 65 - 64
|
||||
*/
|
||||
enum external_pb1200_ints {
|
||||
enum external_db1200_ints {
|
||||
DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
|
||||
|
||||
DB1200_IDE_INT = DB1200_INT_BEGIN,
|
||||
|
|
@ -103,7 +83,4 @@ enum external_pb1200_ints {
|
|||
DB1200_INT_END = DB1200_INT_BEGIN + 15,
|
||||
};
|
||||
|
||||
/* NAND chip select */
|
||||
#define NAND_CS 1
|
||||
|
||||
#endif /* __ASM_DB1200_H */
|
||||
|
|
|
|||
Reference in New Issue