drm/nv50: move tlb flushing to a helper function
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
f56cb86f9a
commit
631872155f
4 changed files with 23 additions and 97 deletions
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@ -1039,6 +1039,7 @@ extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
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extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
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extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
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extern void nv50_instmem_flush(struct drm_device *);
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extern void nv50_vm_flush(struct drm_device *, int engine);
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/* nv04_mc.c */
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extern int nv04_mc_init(struct drm_device *);
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@ -176,34 +176,10 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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}
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dev_priv->engine.instmem.flush(dev);
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00040001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00060001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv50_vm_flush(dev, 5);
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nv50_vm_flush(dev, 0);
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nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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return 0;
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}
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@ -232,32 +208,10 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
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}
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dev_priv->engine.instmem.flush(dev);
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return;
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}
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nv_wr32(dev, 0x100c80, 0x00040001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return;
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}
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nv_wr32(dev, 0x100c80, 0x00060001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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}
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nv50_vm_flush(dev, 5);
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nv50_vm_flush(dev, 0);
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nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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}
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/*
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@ -118,21 +118,8 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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dev_priv->engine.instmem.flush(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv50_vm_flush(dev, 5); /* PGRAPH */
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nv50_vm_flush(dev, 0); /* PFIFO */
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}
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nvbe->bound = true;
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@ -171,21 +158,8 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
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dev_priv->engine.instmem.flush(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv50_vm_flush(dev, 5);
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nv50_vm_flush(dev, 0);
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}
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nvbe->bound = false;
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@ -453,19 +453,8 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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}
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dev_priv->engine.instmem.flush(dev);
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nv_wr32(dev, 0x100c80, 0x00040001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00060001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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gpuobj->im_bound = 1;
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return 0;
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@ -502,3 +491,11 @@ nv50_instmem_flush(struct drm_device *dev)
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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void
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nv50_vm_flush(struct drm_device *dev, int engine)
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{
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nv_wr32(dev, 0x100c80, (engine << 16) | 1);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000))
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NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
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}
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