[BNX2]: Remove CTX_WR macro.
The CTX_WR macro is unnecessary and obfuscates the code. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2726d6e126
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62a8313cdd
2 changed files with 14 additions and 20 deletions
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@ -2237,7 +2237,7 @@ bnx2_init_context(struct bnx2 *bp)
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/* Zero out the context. */
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for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
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CTX_WR(bp, vcid_addr, offset, 0);
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bnx2_ctx_wr(bp, vcid_addr, offset, 0);
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}
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}
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}
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@ -4523,6 +4523,7 @@ static void
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bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
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{
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u32 val, offset0, offset1, offset2, offset3;
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u32 cid_addr = GET_CID_ADDR(cid);
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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offset0 = BNX2_L2CTX_TYPE_XI;
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@ -4536,16 +4537,16 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
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offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
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}
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val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
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CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
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bnx2_ctx_wr(bp, cid_addr, offset0, val);
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val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
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CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
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bnx2_ctx_wr(bp, cid_addr, offset1, val);
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val = (u64) bp->tx_desc_mapping >> 32;
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CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
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bnx2_ctx_wr(bp, cid_addr, offset2, val);
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val = (u64) bp->tx_desc_mapping & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
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bnx2_ctx_wr(bp, cid_addr, offset3, val);
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}
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static void
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@ -4615,21 +4616,21 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
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bp->rx_buf_use_size, bp->rx_max_ring);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
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if (bp->rx_pg_ring_size) {
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bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
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bp->rx_pg_desc_mapping,
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PAGE_SIZE, bp->rx_max_pg_ring);
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val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
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BNX2_L2CTX_RBDC_JUMBO_KEY);
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val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
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val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
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@ -4638,13 +4639,13 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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val |= 0x02 << 8;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
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val = (u64) bp->rx_desc_mapping[0] >> 32;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
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val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
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bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
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ring_prod = prod = bnapi->rx_pg_prod;
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for (i = 0; i < bp->rx_pg_ring_size; i++) {
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@ -6814,13 +6814,6 @@ struct bnx2 {
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#define REG_WR16(bp, offset, val) \
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writew(val, bp->regview + offset)
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/* Indirect context access. Unlike the MBQ_WR, these macros will not
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* trigger a chip event. */
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static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
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#define CTX_WR(bp, cid_addr, offset, val) \
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bnx2_ctx_wr(bp, cid_addr, offset, val)
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struct cpu_reg {
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u32 mode;
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u32 mode_value_halt;
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