MIPS: BCM63XX: Add external irq support for non 6348 CPUs.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maxime Bizon
Ralf Baechle
parent
71a43927b3
commit
6224892c81
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@ -34,6 +34,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#define ext_irq_count 4
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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#define irq_stat_reg PERF_IRQSTAT_6345_REG
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@ -42,6 +45,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#define ext_irq_count 0
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#define ext_irq_cfg_reg1 0
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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#define irq_stat_reg PERF_IRQSTAT_6348_REG
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@ -50,6 +56,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#define ext_irq_count 4
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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#define irq_stat_reg PERF_IRQSTAT_6358_REG
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@ -58,6 +67,9 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
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#define ext_irq_count 4
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
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#define ext_irq_cfg_reg2 0
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#endif
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#if irq_bits == 32
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@ -81,7 +93,9 @@ static inline void bcm63xx_init_irq(void)
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static u32 irq_stat_addr, irq_mask_addr;
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static void (*dispatch_internal)(void);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_count;
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static unsigned int ext_irq_start, ext_irq_end;
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static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
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static void (*internal_irq_mask)(unsigned int irq);
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static void (*internal_irq_unmask)(unsigned int irq);
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@ -107,14 +121,18 @@ static void bcm63xx_init_irq(void)
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irq_stat_addr += PERF_IRQSTAT_6348_REG;
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irq_mask_addr += PERF_IRQMASK_6348_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
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break;
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case BCM6358_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6358_REG;
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irq_mask_addr += PERF_IRQMASK_6358_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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break;
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default:
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BUG();
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@ -132,6 +150,13 @@ static void bcm63xx_init_irq(void)
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}
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#endif /* ! BCMCPU_RUNTIME_DETECT */
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static inline u32 get_ext_irq_perf_reg(int irq)
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{
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if (irq < 4)
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return ext_irq_cfg_reg1;
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return ext_irq_cfg_reg2;
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}
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static inline void handle_internal(int intbit)
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{
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if (is_ext_irq_cascaded &&
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@ -273,11 +298,17 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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static void bcm63xx_external_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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u32 reg, regaddr;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg &= ~EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
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else
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reg &= ~EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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if (is_ext_irq_cascaded)
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internal_irq_mask(irq + ext_irq_start);
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}
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@ -285,11 +316,18 @@ static void bcm63xx_external_irq_mask(struct irq_data *d)
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static void bcm63xx_external_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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u32 reg, regaddr;
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
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else
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reg |= EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg |= EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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if (is_ext_irq_cascaded)
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internal_irq_unmask(irq + ext_irq_start);
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}
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@ -297,58 +335,93 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d)
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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u32 reg, regaddr;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg |= EXTIRQ_CFG_CLEAR(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
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else
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reg |= EXTIRQ_CFG_CLEAR(irq % 4);
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bcm_perf_writel(reg, regaddr);
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}
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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u32 reg, regaddr;
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int levelsense, sense, bothedge;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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levelsense = sense = bothedge = 0;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_BOTH:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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bothedge = 1;
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break;
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case IRQ_TYPE_EDGE_RISING:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_SENSE(irq);
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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sense = 1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_SENSE(irq);
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levelsense = 1;
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sense = 1;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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levelsense = 1;
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break;
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default:
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printk(KERN_ERR "bogus flow type combination given !\n");
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return -EINVAL;
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}
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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irq %= 4;
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if (BCMCPU_IS_6348()) {
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
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if (sense)
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reg |= EXTIRQ_CFG_SENSE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
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if (bothedge)
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reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
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}
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if (BCMCPU_IS_6338() || BCMCPU_IS_6358()) {
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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else
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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if (sense)
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reg |= EXTIRQ_CFG_SENSE(irq);
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else
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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if (bothedge)
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reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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}
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bcm_perf_writel(reg, regaddr);
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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@ -397,12 +470,12 @@ void __init arch_init_irq(void)
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irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
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handle_level_irq);
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for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + 4; ++i)
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for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
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irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
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handle_edge_irq);
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if (!is_ext_irq_cascaded) {
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for (i = 3; i < 7; ++i)
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for (i = 3; i < 3 + ext_irq_count; ++i)
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setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
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}
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@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
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void bcm63xx_machine_reboot(void)
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{
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u32 reg;
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u32 reg, perf_regs[2] = { 0, 0 };
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unsigned int i;
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/* mask and clear all external irq */
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg &= ~EXTIRQ_CFG_MASK_ALL;
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reg |= EXTIRQ_CFG_CLEAR_ALL;
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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switch (bcm63xx_get_cpu_id()) {
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case BCM6338_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
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break;
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case BCM6348_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
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break;
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case BCM6358_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
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break;
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}
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for (i = 0; i < 2; i++) {
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reg = bcm_perf_readl(perf_regs[i]);
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if (BCMCPU_IS_6348()) {
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reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
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reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
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} else {
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reg &= ~EXTIRQ_CFG_MASK_ALL;
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reg |= EXTIRQ_CFG_CLEAR_ALL;
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}
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bcm_perf_writel(reg, perf_regs[i]);
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}
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if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
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bcm6348_a1_reboot();
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@ -100,16 +100,29 @@
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#define PERF_IRQSTAT_6358_REG 0x10
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/* External Interrupt Configuration register */
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#define PERF_EXTIRQ_CFG_REG 0x14
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#define EXTIRQ_CFG_SENSE(x) (1 << (x))
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#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
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#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
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#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
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#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
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#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
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#define PERF_EXTIRQ_CFG_REG_6338 0x14
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#define PERF_EXTIRQ_CFG_REG_6348 0x14
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#define PERF_EXTIRQ_CFG_REG_6358 0x14
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#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
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#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
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/* for 6348 only */
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#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
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#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
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#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
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#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
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#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
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#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
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#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
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#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
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/* for all others */
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#define EXTIRQ_CFG_SENSE(x) (1 << (x))
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#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
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#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
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#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
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#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
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#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
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#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
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#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
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/* Soft Reset register */
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#define PERF_SOFTRESET_REG 0x28
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