CRIS: GENERIC_TIME fixes
GENERIC_TIME was not functional for CRIS, giving random backward time jumps. For CRISv32 implement a new clocksource using the free running counter and ditch the arch_gettimeoffset. The random time jumps still existed, but turned out to be the write_seqlock which was missing around our do_timer() call. So switch over to GENERIC_TIME using the clocksource for CRISv32. CRISv10 doesn't have the free running counter needed for the clocksource trick, but we can still use GENERIC_TIME with arch_gettimeoffset. Unfortunately, there were problems in using the prescaler register to timer0 for the gettimeoffset calculation, so it is now ignored, making our resolution worse by the tune of 40usec (0.4%) worst case. At the same time, clean up some formatting and use NSEC_PER_SEC instead of 1000000000. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
This commit is contained in:
Jesper Nilsson
parent
26bfeea38a
commit
60dbd66331
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@ -27,7 +27,7 @@ config GENERIC_CMOS_UPDATE
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def_bool y
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config ARCH_USES_GETTIMEOFFSET
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def_bool y
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def_bool n
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config GENERIC_IOMAP
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bool
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@ -131,16 +131,19 @@ choice
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config ETRAX100LX
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bool "ETRAX-100LX-v1"
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select ARCH_USES_GETTIMEOFFSET
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help
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Support version 1 of the ETRAX 100LX.
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config ETRAX100LX_V2
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bool "ETRAX-100LX-v2"
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select ARCH_USES_GETTIMEOFFSET
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help
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Support version 2 of the ETRAX 100LX.
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config SVINTO_SIM
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bool "ETRAX-100LX-for-xsim-simulator"
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select ARCH_USES_GETTIMEOFFSET
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help
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Support the xsim ETRAX Simulator.
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@ -61,66 +61,16 @@ unsigned long get_ns_in_jiffie(void)
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unsigned long do_slow_gettimeoffset(void)
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{
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unsigned long count, t1;
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unsigned long usec_count = 0;
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unsigned short presc_count;
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static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
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static unsigned long jiffies_p = 0;
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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unsigned long jiffies_t;
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unsigned long count;
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/* The timer interrupt comes from Etrax timer 0. In order to get
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* better precision, we check the current value. It might have
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* underflowed already though.
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*/
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#ifndef CONFIG_SVINTO_SIM
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/* Not available in the xsim simulator. */
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count = *R_TIMER0_DATA;
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presc_count = *R_TIM_PRESC_STATUS;
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/* presc_count might be wrapped */
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t1 = *R_TIMER0_DATA;
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if (count != t1){
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/* it wrapped, read prescaler again... */
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presc_count = *R_TIM_PRESC_STATUS;
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count = t1;
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}
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#else
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count = 0;
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presc_count = 0;
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#endif
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jiffies_t = jiffies;
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/*
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* avoiding timer inconsistencies (they are rare, but they happen)...
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* there are one problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if( jiffies_t == jiffies_p ) {
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if( count > count_p ) {
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/* Timer wrapped, use new count and prescale
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* increase the time corresponding to one jiffie
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*/
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usec_count = 1000000/HZ;
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}
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} else
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jiffies_p = jiffies_t;
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count_p = count;
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if (presc_count >= PRESCALE_VALUE/2 ){
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presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
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} else {
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presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
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}
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/* Convert timer value to usec */
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usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
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(( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
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return usec_count;
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return (TIMER0_DIV - count) * ((NSEC_PER_SEC/1000)/HZ)/TIMER0_DIV;
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}
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/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
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@ -1,13 +1,13 @@
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/*
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* linux/arch/cris/arch-v32/kernel/time.c
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*
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* Copyright (C) 2003-2007 Axis Communications AB
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* Copyright (C) 2003-2010 Axis Communications AB
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*
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*/
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#include <linux/timex.h>
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#include <linux/time.h>
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#include <linux/jiffies.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/swap.h>
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#include <linux/sched.h>
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@ -36,6 +36,30 @@
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/* Number of 763 counts before watchdog bites */
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#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
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/* Register the continuos readonly timer available in FS and ARTPEC-3. */
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static cycle_t read_cont_rotime(struct clocksource *cs)
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{
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return (u32)REG_RD(timer, regi_timer0, r_time);
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}
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static struct clocksource cont_rotime = {
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.name = "crisv32_rotime",
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.rating = 300,
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.read = read_cont_rotime,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init etrax_init_cont_rotime(void)
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{
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cont_rotime.mult = clocksource_khz2mult(100000, cont_rotime.shift);
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clocksource_register(&cont_rotime);
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return 0;
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}
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arch_initcall(etrax_init_cont_rotime);
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unsigned long timer_regs[NR_CPUS] =
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{
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regi_timer0,
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@ -67,43 +91,6 @@ unsigned long get_ns_in_jiffie(void)
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return ns;
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}
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unsigned long do_slow_gettimeoffset(void)
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{
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unsigned long count;
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unsigned long usec_count = 0;
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/* For the first call after boot */
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static unsigned long count_p = TIMER0_DIV;
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static unsigned long jiffies_p = 0;
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/* Cache volatile jiffies temporarily; we have IRQs turned off. */
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unsigned long jiffies_t;
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/* The timer interrupt comes from Etrax timer 0. In order to get
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* better precision, we check the current value. It might have
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* underflowed already though. */
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count = REG_RD(timer, regi_timer0, r_tmr0_data);
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jiffies_t = jiffies;
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/* Avoiding timer inconsistencies (they are rare, but they happen)
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* There is one problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if( jiffies_t == jiffies_p ) {
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if( count > count_p ) {
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/* Timer wrapped, use new count and prescale.
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* Increase the time corresponding to one jiffy.
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*/
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usec_count = 1000000/HZ;
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}
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} else
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jiffies_p = jiffies_t;
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count_p = count;
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/* Convert timer value to usec */
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/* 100 MHz timer, divide by 100 to get usec */
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usec_count += (TIMER0_DIV - count) / 100;
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return usec_count;
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}
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/* From timer MDS describing the hardware watchdog:
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* 4.3.1 Watchdog Operation
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@ -126,8 +113,7 @@ static short int watchdog_key = 42; /* arbitrary 7 bit number */
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* is used though, so set this really low. */
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#define WATCHDOG_MIN_FREE_PAGES 8
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void
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reset_watchdog(void)
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void reset_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
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@ -147,8 +133,7 @@ reset_watchdog(void)
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/* stop the watchdog - we still need the correct key */
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void
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stop_watchdog(void)
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void stop_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
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@ -162,8 +147,7 @@ stop_watchdog(void)
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extern void show_registers(struct pt_regs *regs);
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void
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handle_watchdog_bite(struct pt_regs* regs)
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void handle_watchdog_bite(struct pt_regs *regs)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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extern int cause_of_death;
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@ -203,8 +187,7 @@ handle_watchdog_bite(struct pt_regs* regs)
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*/
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extern void cris_do_profile(struct pt_regs *regs);
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static inline irqreturn_t
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timer_interrupt(int irq, void *dev_id)
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static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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int cpu = smp_processor_id();
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@ -233,7 +216,9 @@ timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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/* Call the real timer interrupt handler */
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write_seqlock(&xtime_lock);
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do_timer(1);
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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@ -246,8 +231,7 @@ static struct irqaction irq_timer = {
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.name = "timer"
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};
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void __init
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cris_timer_init(void)
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void __init cris_timer_init(void)
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{
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int cpu = smp_processor_id();
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reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
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@ -273,8 +257,7 @@ cris_timer_init(void)
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REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
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}
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void __init
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time_init(void)
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void __init time_init(void)
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{
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reg_intr_vect_rw_mask intr_mask;
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@ -39,13 +39,16 @@ int have_rtc; /* used to remember if we have an RTC or not */;
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extern unsigned long loops_per_jiffy; /* init/main.c */
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unsigned long loops_per_usec;
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#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
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extern unsigned long do_slow_gettimeoffset(void);
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static unsigned long (*do_gettimeoffset)(void) = do_slow_gettimeoffset;
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u32 arch_gettimeoffset(void)
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{
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return do_gettimeoffset() * 1000;
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return do_gettimeoffset() * 1000;
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}
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#endif
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/*
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* BUG: This routine does not handle hour overflow properly; it just
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@ -151,7 +154,7 @@ cris_do_profile(struct pt_regs* regs)
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unsigned long long sched_clock(void)
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{
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return (unsigned long long)jiffies * (1000000000 / HZ) +
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return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ) +
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get_ns_in_jiffie();
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}
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