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pinctrl: mvebu: add pinctrl driver for Armada 370 

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Petazzoni 2012-09-13 17:41:46 +02:00 committed by Jason Cooper
parent 9d4b1632bc
commit 5f597bb2be
4 changed files with 521 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

95
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt Normal file
View File

@ -0,0 +1,95 @@
* Marvell Armada 370 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, uart0(rxd)
mpp1 1 gpo, uart0(txd)
mpp2 2 gpio, i2c0(sck), uart0(txd)
mpp3 3 gpio, i2c0(sda), uart0(rxd)
mpp4 4 gpio, cpu_pd(vdd)
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
sata1(prsnt), spi1(cs1)
mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
audio(spdifi)
mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
audio(rmclk)
mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
spi0(cs2)
mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
spi0(cs3)
mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
mpp17 17 gpo, ge(mdc)
mpp18 18 gpio, ge(mdio)
mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
mpp20 20 gpo, ge0(txd4), ge1(txd0)
mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
mpp31 31 gpio, tclk, ge0(txerr)
mpp32 32 gpio, spi0(cs0)
mpp33 33 gpio, dev(bootcs), spi0(cs0)
mpp34 34 gpo, dev(wen0), spi0(mosi)
mpp35 35 gpo, dev(oen), spi0(sck)
mpp36 36 gpo, dev(a1), spi0(miso)
mpp37 37 gpo, dev(a0), sata0(prsnt)
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
mpp39 39 gpo, dev(ad0), audio(spdifo)
mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
mpp41 41 gpio, dev(ad2), uart1(rxd)
mpp42 42 gpo, dev(ad3), uart1(txd)
mpp43 43 gpo, dev(ad4), audio(bclk)
mpp44 44 gpo, dev(ad5), audio(mclk)
mpp45 45 gpo, dev(ad6), audio(lrclk)
mpp46 46 gpo, dev(ad7), audio(sdo)
mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
spi0(cs1)
mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
audio(spdifi)
mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
audio(rmclk)
mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
pcie(clkreq1)
mpp54 54 gpo, dev(ad15), tdm(dtx)
mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
sata0(prsnt)
mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
pcie(clkreq0), spi1(cs1)
mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
audio(sdo)
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
uart0(rts)
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
audio(sdi)
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
audio(mclk), uart0(cts)
mpp63 63 gpo, spi0(sck), tclk
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)

4
drivers/pinctrl/Kconfig
View File

@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
bool
select PINCTRL_MVEBU
config PINCTRL_ARMADA_370
bool
select PINCTRL_MVEBU
source "drivers/pinctrl/spear/Kconfig"
endmenu

1
drivers/pinctrl/Makefile
View File

@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
obj-$(CONFIG_PLAT_SPEAR) += spear/

421
drivers/pinctrl/pinctrl-armada-370.c Normal file
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@ -0,0 +1,421 @@
/*
* Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "uart0", "rxd")),
MPP_MODE(1,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "uart0", "txd")),
MPP_MODE(2,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c0", "sck"),
MPP_FUNCTION(0x2, "uart0", "txd")),
MPP_MODE(3,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c0", "sda"),
MPP_FUNCTION(0x2, "uart0", "rxd")),
MPP_MODE(4,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
MPP_MODE(5,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txclko"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x4, "spi1", "clk"),
MPP_FUNCTION(0x5, "audio", "mclk")),
MPP_MODE(6,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txd0"),
MPP_FUNCTION(0x2, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "tdm", "rst"),
MPP_FUNCTION(0x5, "audio", "sdo")),
MPP_MODE(7,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd1"),
MPP_FUNCTION(0x4, "tdm", "tdx"),
MPP_FUNCTION(0x5, "audio", "lrclk")),
MPP_MODE(8,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txd2"),
MPP_FUNCTION(0x2, "uart0", "rts"),
MPP_FUNCTION(0x4, "tdm", "drx"),
MPP_FUNCTION(0x5, "audio", "bclk")),
MPP_MODE(9,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd3"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x3, "sd0", "clk"),
MPP_FUNCTION(0x5, "audio", "spdifo")),
MPP_MODE(10,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txctl"),
MPP_FUNCTION(0x2, "uart0", "cts"),
MPP_FUNCTION(0x4, "tdm", "fsync"),
MPP_FUNCTION(0x5, "audio", "sdi")),
MPP_MODE(11,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd0"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "sd0", "cmd"),
MPP_FUNCTION(0x4, "spi0", "cs1"),
MPP_FUNCTION(0x5, "sata1", "prsnt"),
MPP_FUNCTION(0x6, "spi1", "cs1")),
MPP_MODE(12,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd1"),
MPP_FUNCTION(0x2, "i2c1", "sda"),
MPP_FUNCTION(0x3, "sd0", "d0"),
MPP_FUNCTION(0x4, "spi1", "cs0"),
MPP_FUNCTION(0x5, "audio", "spdifi")),
MPP_MODE(13,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd2"),
MPP_FUNCTION(0x2, "i2c1", "sck"),
MPP_FUNCTION(0x3, "sd0", "d1"),
MPP_FUNCTION(0x4, "tdm", "pclk"),
MPP_FUNCTION(0x5, "audio", "rmclk")),
MPP_MODE(14,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd3"),
MPP_FUNCTION(0x2, "pcie", "clkreq0"),
MPP_FUNCTION(0x3, "sd0", "d2"),
MPP_FUNCTION(0x4, "spi1", "mosi"),
MPP_FUNCTION(0x5, "spi0", "cs2")),
MPP_MODE(15,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxctl"),
MPP_FUNCTION(0x2, "pcie", "clkreq1"),
MPP_FUNCTION(0x3, "sd0", "d3"),
MPP_FUNCTION(0x4, "spi1", "miso"),
MPP_FUNCTION(0x5, "spi0", "cs3")),
MPP_MODE(16,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxclk"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x4, "tdm", "int"),
MPP_FUNCTION(0x5, "audio", "extclk")),
MPP_MODE(17,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge", "mdc")),
MPP_MODE(18,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge", "mdio")),
MPP_MODE(19,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txclk"),
MPP_FUNCTION(0x2, "ge1", "txclkout"),
MPP_FUNCTION(0x4, "tdm", "pclk")),
MPP_MODE(20,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd4"),
MPP_FUNCTION(0x2, "ge1", "txd0")),
MPP_MODE(21,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd5"),
MPP_FUNCTION(0x2, "ge1", "txd1"),
MPP_FUNCTION(0x4, "uart1", "txd")),
MPP_MODE(22,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd6"),
MPP_FUNCTION(0x2, "ge1", "txd2"),
MPP_FUNCTION(0x4, "uart0", "rts")),
MPP_MODE(23,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd7"),
MPP_FUNCTION(0x2, "ge1", "txd3"),
MPP_FUNCTION(0x4, "spi1", "mosi")),
MPP_MODE(24,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "col"),
MPP_FUNCTION(0x2, "ge1", "txctl"),
MPP_FUNCTION(0x4, "spi1", "cs0")),
MPP_MODE(25,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxerr"),
MPP_FUNCTION(0x2, "ge1", "rxd0"),
MPP_FUNCTION(0x4, "uart1", "rxd")),
MPP_MODE(26,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "crs"),
MPP_FUNCTION(0x2, "ge1", "rxd1"),
MPP_FUNCTION(0x4, "spi1", "miso")),
MPP_MODE(27,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd4"),
MPP_FUNCTION(0x2, "ge1", "rxd2"),
MPP_FUNCTION(0x4, "uart0", "cts")),
MPP_MODE(28,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd5"),
MPP_FUNCTION(0x2, "ge1", "rxd3")),
MPP_MODE(29,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd6"),
MPP_FUNCTION(0x2, "ge1", "rxctl"),
MPP_FUNCTION(0x4, "i2c1", "sda")),
MPP_MODE(30,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd7"),
MPP_FUNCTION(0x2, "ge1", "rxclk"),
MPP_FUNCTION(0x4, "i2c1", "sck")),
MPP_MODE(31,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x3, "tclk", NULL),
MPP_FUNCTION(0x4, "ge0", "txerr")),
MPP_MODE(32,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "cs0")),
MPP_MODE(33,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "bootcs"),
MPP_FUNCTION(0x2, "spi0", "cs0")),
MPP_MODE(34,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "wen0"),
MPP_FUNCTION(0x2, "spi0", "mosi")),
MPP_MODE(35,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "oen"),
MPP_FUNCTION(0x2, "spi0", "sck")),
MPP_MODE(36,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "a1"),
MPP_FUNCTION(0x2, "spi0", "miso")),
MPP_MODE(37,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "a0"),
MPP_FUNCTION(0x2, "sata0", "prsnt")),
MPP_MODE(38,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ready"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "uart0", "cts")),
MPP_MODE(39,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad0"),
MPP_FUNCTION(0x2, "audio", "spdifo")),
MPP_MODE(40,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad1"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "uart0", "rts")),
MPP_MODE(41,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad2"),
MPP_FUNCTION(0x2, "uart1", "rxd")),
MPP_MODE(42,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad3"),
MPP_FUNCTION(0x2, "uart1", "txd")),
MPP_MODE(43,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad4"),
MPP_FUNCTION(0x2, "audio", "bclk")),
MPP_MODE(44,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad5"),
MPP_FUNCTION(0x2, "audio", "mclk")),
MPP_MODE(45,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad6"),
MPP_FUNCTION(0x2, "audio", "lrclk")),
MPP_MODE(46,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad7"),
MPP_FUNCTION(0x2, "audio", "sdo")),
MPP_MODE(47,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad8"),
MPP_FUNCTION(0x3, "sd0", "clk"),
MPP_FUNCTION(0x5, "audio", "spdifo")),
MPP_MODE(48,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad9"),
MPP_FUNCTION(0x2, "uart0", "rts"),
MPP_FUNCTION(0x3, "sd0", "cmd"),
MPP_FUNCTION(0x4, "sata1", "prsnt"),
MPP_FUNCTION(0x5, "spi0", "cs1")),
MPP_MODE(49,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad10"),
MPP_FUNCTION(0x2, "pcie", "clkreq1"),
MPP_FUNCTION(0x3, "sd0", "d0"),
MPP_FUNCTION(0x4, "spi1", "cs0"),
MPP_FUNCTION(0x5, "audio", "spdifi")),
MPP_MODE(50,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad11"),
MPP_FUNCTION(0x2, "uart0", "cts"),
MPP_FUNCTION(0x3, "sd0", "d1"),
MPP_FUNCTION(0x4, "spi1", "miso"),
MPP_FUNCTION(0x5, "audio", "rmclk")),
MPP_MODE(51,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad12"),
MPP_FUNCTION(0x2, "i2c1", "sda"),
MPP_FUNCTION(0x3, "sd0", "d2"),
MPP_FUNCTION(0x4, "spi1", "mosi")),
MPP_MODE(52,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad13"),
MPP_FUNCTION(0x2, "i2c1", "sck"),
MPP_FUNCTION(0x3, "sd0", "d3"),
MPP_FUNCTION(0x4, "spi1", "sck")),
MPP_MODE(53,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad14"),
MPP_FUNCTION(0x2, "sd0", "clk"),
MPP_FUNCTION(0x3, "tdm", "pclk"),
MPP_FUNCTION(0x4, "spi0", "cs2"),
MPP_FUNCTION(0x5, "pcie", "clkreq1")),
MPP_MODE(54,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad15"),
MPP_FUNCTION(0x3, "tdm", "dtx")),
MPP_MODE(55,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs1"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x3, "tdm", "rst"),
MPP_FUNCTION(0x4, "sata1", "prsnt"),
MPP_FUNCTION(0x5, "sata0", "prsnt")),
MPP_MODE(56,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs2"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "uart0", "cts"),
MPP_FUNCTION(0x4, "spi0", "cs3"),
MPP_FUNCTION(0x5, "pcie", "clkreq0"),
MPP_FUNCTION(0x6, "spi1", "cs1")),
MPP_MODE(57,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs3"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "tdm", "fsync"),
MPP_FUNCTION(0x4, "sata0", "prsnt"),
MPP_FUNCTION(0x5, "audio", "sdo")),
MPP_MODE(58,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs0"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "tdm", "int"),
MPP_FUNCTION(0x5, "audio", "extclk"),
MPP_FUNCTION(0x6, "uart0", "rts")),
MPP_MODE(59,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ale0"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "uart0", "rts"),
MPP_FUNCTION(0x5, "audio", "bclk")),
MPP_MODE(60,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ale1"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "pcie", "rst-out"),
MPP_FUNCTION(0x5, "audio", "sdi")),
MPP_MODE(61,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "wen1"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x5, "audio", "rclk")),
MPP_MODE(62,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "a2"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "tdm", "drx"),
MPP_FUNCTION(0x4, "pcie", "clkreq0"),
MPP_FUNCTION(0x5, "audio", "mclk"),
MPP_FUNCTION(0x6, "uart0", "cts")),
MPP_MODE(63,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "spi0", "sck"),
MPP_FUNCTION(0x2, "tclk", NULL)),
MPP_MODE(64,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "miso"),
MPP_FUNCTION(0x2, "spi0-1", "cs1")),
MPP_MODE(65,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "mosi"),
MPP_FUNCTION(0x2, "spi0-1", "cs2")),
};
static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
{ .compatible = "marvell,mv88f6710-pinctrl" },
{ },
};
static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
MPP_REG_CTRL(0, 65),
};
static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 2),
};
static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
soc->variant = 0; /* no variants for Armada 370 */
soc->controls = mv88f6710_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
soc->modes = mv88f6710_mpp_modes;
soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
soc->gpioranges = mv88f6710_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
pdev->dev.platform_data = soc;
return mvebu_pinctrl_probe(pdev);
}
static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
{
return mvebu_pinctrl_remove(pdev);
}
static struct platform_driver armada_370_pinctrl_driver = {
.driver = {
.name = "armada-370-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
},
.probe = armada_370_pinctrl_probe,
.remove = __devexit_p(armada_370_pinctrl_remove),
};
module_platform_driver(armada_370_pinctrl_driver);
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
MODULE_LICENSE("GPL v2");