From 5f1545bc45a33361d6bb2fb44af7c35bcd733b9d Mon Sep 17 00:00:00 2001 From: Joachim Deguara Date: Fri, 16 Mar 2007 15:01:36 +0100 Subject: [PATCH] [ALSA] hda-intel - Fix HDA buffer alignment From the HDA spec it appears that the buffers written to the BDL and sent to a codec must be 128 byte aligned (section 4.5.1). The alignment was not happening especially when playing 6 channels. This patch set the alignment of buffers and periods to 128 bytes. Signed-off-by: Joachim Deguara Signed-off-by: Takashi Iwai Signed-off-by: Jaroslav Kysela --- sound/pci/hda/hda_intel.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 13e4837b5ae..1672cace1ae 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1087,6 +1087,10 @@ static int azx_pcm_open(struct snd_pcm_substream *substream) runtime->hw.rates = hinfo->rates; snd_pcm_limit_hw_rates(runtime); snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, + 128); + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + 128); if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { azx_release_device(azx_dev); mutex_unlock(&chip->open_mutex);