From f50266d3139a0e8a26f6f387c91816ab60dac0b4 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 25 Nov 2010 14:17:01 +0900 Subject: [PATCH 1/7] ARM: S5P64X0: Add GPIOlib support for S5P6450 Already can support S5P6440 GPIOlib but S5P6450. This patch changes regarding S5P6440 GPIO definitions so that can be used it from S5P6450 and adds S5P6450 GPIO chips. Tested-by: Atul Dahiya Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/Makefile | 4 +- arch/arm/mach-s5p64x0/gpio.c | 224 ++++++++++++++++-- .../arm/mach-s5p64x0/include/mach/regs-gpio.h | 55 ++--- 3 files changed, 216 insertions(+), 67 deletions(-) diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index 2655829e6bf..835d51b328f 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile @@ -12,9 +12,9 @@ obj- := # Core support for S5P64X0 system -obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o +obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpio.o obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o -obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o +obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o # machine support diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpio.c index 39159dd5a29..17a2eee3da7 100644 --- a/arch/arm/mach-s5p64x0/gpio.c +++ b/arch/arm/mach-s5p64x0/gpio.c @@ -17,13 +17,12 @@ #include #include +#include #include #include #include -/* To be implemented S5P6450 GPIO */ - /* * S5P6440 GPIO bank summary: * @@ -40,6 +39,25 @@ * P 8 2Bit Yes 8 * R 15 4Bit[2] Yes 8 * + * S5P6450 GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 6 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 8 4Bit Yes None + * F 2 2Bit Yes None + * G 14 4Bit[2] Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 5 4Bit Yes None + * N 16 2Bit No IRQ_EINT + * P 11 2Bit Yes 8 + * Q 14 2Bit Yes None + * R 15 4Bit[2] Yes None + * S 8 2Bit Yes None + * * [1] BANKF pins 14,15 do not form part of the external interrupt sources * [2] BANK has two control registers, GPxCON0 and GPxCON1 */ @@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = { static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { { - .base = S5P6440_GPA_BASE, + .base = S5P64X0_GPA_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPA(0), @@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPA", }, }, { - .base = S5P6440_GPB_BASE, + .base = S5P64X0_GPB_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPB(0), @@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPB", }, }, { - .base = S5P6440_GPC_BASE, + .base = S5P64X0_GPC_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPC(0), @@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPC", }, }, { - .base = S5P6440_GPG_BASE, + .base = S5P64X0_GPG_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPG(0), @@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { { - .base = S5P6440_GPH_BASE + 0x4, + .base = S5P64X0_GPH_BASE + 0x4, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPH(0), @@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { { - .base = S5P6440_GPR_BASE + 0x4, + .base = S5P64X0_GPR_BASE + 0x4, .config = &s5p64x0_gpio_cfgs[2], .chip = { .base = S5P6440_GPR(0), @@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { { - .base = S5P6440_GPF_BASE, + .base = S5P64X0_GPF_BASE, .config = &s5p64x0_gpio_cfgs[5], .chip = { .base = S5P6440_GPF(0), @@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPF", }, }, { - .base = S5P6440_GPI_BASE, + .base = S5P64X0_GPI_BASE, .config = &s5p64x0_gpio_cfgs[3], .chip = { .base = S5P6440_GPI(0), @@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPI", }, }, { - .base = S5P6440_GPJ_BASE, + .base = S5P64X0_GPJ_BASE, .config = &s5p64x0_gpio_cfgs[3], .chip = { .base = S5P6440_GPJ(0), @@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPJ", }, }, { - .base = S5P6440_GPN_BASE, + .base = S5P64X0_GPN_BASE, .config = &s5p64x0_gpio_cfgs[4], .chip = { .base = S5P6440_GPN(0), @@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPN", }, }, { - .base = S5P6440_GPP_BASE, + .base = S5P64X0_GPP_BASE, .config = &s5p64x0_gpio_cfgs[5], .chip = { .base = S5P6440_GPP(0), @@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { }, }; +static struct s3c_gpio_chip s5p6450_gpio_4bit[] = { + { + .base = S5P64X0_GPA_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPA(0), + .ngpio = S5P6450_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S5P64X0_GPB_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPB(0), + .ngpio = S5P6450_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S5P64X0_GPC_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPC(0), + .ngpio = S5P6450_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5P6450_GPD_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPD(0), + .ngpio = S5P6450_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S5P6450_GPK_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPK(0), + .ngpio = S5P6450_GPIO_K_NR, + .label = "GPK", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = { + { + .base = S5P64X0_GPG_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPG(0), + .ngpio = S5P6450_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S5P64X0_GPH_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPH(0), + .ngpio = S5P6450_GPIO_H_NR, + .label = "GPH", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = { + { + .base = S5P64X0_GPR_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[2], + .chip = { + .base = S5P6450_GPR(0), + .ngpio = S5P6450_GPIO_R_NR, + .label = "GPR", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_2bit[] = { + { + .base = S5P64X0_GPF_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPF(0), + .ngpio = S5P6450_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P64X0_GPI_BASE, + .config = &s5p64x0_gpio_cfgs[3], + .chip = { + .base = S5P6450_GPI(0), + .ngpio = S5P6450_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P64X0_GPJ_BASE, + .config = &s5p64x0_gpio_cfgs[3], + .chip = { + .base = S5P6450_GPJ(0), + .ngpio = S5P6450_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P64X0_GPN_BASE, + .config = &s5p64x0_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPN(0), + .ngpio = S5P6450_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P64X0_GPP_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPP(0), + .ngpio = S5P6450_GPIO_P_NR, + .label = "GPP", + }, + }, { + .base = S5P6450_GPQ_BASE, + .config = &s5p64x0_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPQ(0), + .ngpio = S5P6450_GPIO_Q_NR, + .label = "GPQ", + }, + }, { + .base = S5P6450_GPS_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPS(0), + .ngpio = S5P6450_GPIO_S_NR, + .label = "GPS", + }, + }, +}; + void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) { for (; nr_chips > 0; nr_chips--, chipcfg++) { @@ -317,26 +471,46 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, } } -static int __init s5p6440_gpiolib_init(void) +static int __init s5p64x0_gpiolib_init(void) { - struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; - int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); + struct s3c_gpio_chip *s5p6440_chips = s5p6440_gpio_2bit; + int s5p6440_nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); + + struct s3c_gpio_chip *s5p6450_chips = s5p6450_gpio_2bit; + int s5p6450_nr_chips = ARRAY_SIZE(s5p6450_gpio_2bit); + + unsigned int chipid; s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, ARRAY_SIZE(s5p64x0_gpio_cfgs)); + chipid = __raw_readl(S5P64X0_SYS_ID); - for (; nr_chips > 0; nr_chips--, chips++) - s3c_gpiolib_add(chips); + if ((chipid & 0xff000) == 0x50000) { + for (; s5p6450_nr_chips > 0; s5p6450_nr_chips--, s5p6450_chips++) + s3c_gpiolib_add(s5p6450_chips); - samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, - ARRAY_SIZE(s5p6440_gpio_4bit)); + samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit, + ARRAY_SIZE(s5p6450_gpio_4bit)); - samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, - ARRAY_SIZE(s5p6440_gpio_4bit2)); + samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2, + ARRAY_SIZE(s5p6450_gpio_4bit2)); - s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, - ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); + s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2, + ARRAY_SIZE(s5p6450_gpio_rbank_4bit2)); + } else { + for (; s5p6440_nr_chips > 0; s5p6440_nr_chips--, s5p6440_chips++) + s3c_gpiolib_add(s5p6440_chips); + + samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, + ARRAY_SIZE(s5p6440_gpio_4bit)); + + samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, + ARRAY_SIZE(s5p6440_gpio_4bit2)); + + s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, + ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); + } return 0; } -arch_initcall(s5p6440_gpiolib_init); +arch_initcall(s5p64x0_gpiolib_init); diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h index 85f448e20a8..0953ef6b1c7 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h @@ -15,48 +15,23 @@ #include -/* Will be implemented S5P6442 GPIOlib */ - /* Base addresses for each of the banks */ -#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) -#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) -#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) -#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) -#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) -#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) -#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) -#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) -#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) -#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) -#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) +#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000) +#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020) +#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040) +#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0) +#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0) +#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0) +#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100) +#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120) +#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830) +#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160) +#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290) -#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) -#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) -#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) -#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) -#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) - -/* for LCD */ - -#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) -#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) - -/* - * These set of macros are not really useful for the - * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit) - */ - -#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) -#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) -#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) - -/* - * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) - */ - -#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) -#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) -#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) +#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060) +#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140) +#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) +#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) #endif /* __ASM_ARCH_REGS_GPIO_H */ From 4603089d7c5186d255c4718171187d00ee4d3452 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Nov 2010 10:59:57 +0900 Subject: [PATCH 2/7] ARM: SAMSUNG: Cleanup GPIOlib adding 2bit chips This patch adds samsung_gpiolib_add_2bit_chips() for cleanup regarding GPIOlib adding 2bit chips. Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/gpiolib.c | 7 +++++++ arch/arm/plat-samsung/include/plat/gpio-core.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c index c354089254f..ea37c046178 100644 --- a/arch/arm/plat-samsung/gpiolib.c +++ b/arch/arm/plat-samsung/gpiolib.c @@ -197,3 +197,10 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, s3c_gpiolib_add(chip); } } + +void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) + s3c_gpiolib_add(chip); +} diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 13a22b8861e..dac35d0a711 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -118,6 +118,8 @@ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, int nr_chips); extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, int nr_chips); +extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); From bb1d7002bbfd1471368e1c830a1e6ddcfdff1767 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Nov 2010 11:00:16 +0900 Subject: [PATCH 3/7] ARM: S5P64X0: Cleanup S5P64X0 GPIOlib adding 2bit chips This patch changes S5P6440 and S5P6450 GPIOlib adding 2bit chips. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/gpio.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpio.c index 17a2eee3da7..0670fcceed4 100644 --- a/arch/arm/mach-s5p64x0/gpio.c +++ b/arch/arm/mach-s5p64x0/gpio.c @@ -473,21 +473,16 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, static int __init s5p64x0_gpiolib_init(void) { - struct s3c_gpio_chip *s5p6440_chips = s5p6440_gpio_2bit; - int s5p6440_nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); - - struct s3c_gpio_chip *s5p6450_chips = s5p6450_gpio_2bit; - int s5p6450_nr_chips = ARRAY_SIZE(s5p6450_gpio_2bit); - unsigned int chipid; + chipid = __raw_readl(S5P64X0_SYS_ID); + s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, ARRAY_SIZE(s5p64x0_gpio_cfgs)); - chipid = __raw_readl(S5P64X0_SYS_ID); if ((chipid & 0xff000) == 0x50000) { - for (; s5p6450_nr_chips > 0; s5p6450_nr_chips--, s5p6450_chips++) - s3c_gpiolib_add(s5p6450_chips); + samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, + ARRAY_SIZE(s5p6450_gpio_2bit)); samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit, ARRAY_SIZE(s5p6450_gpio_4bit)); @@ -498,8 +493,8 @@ static int __init s5p64x0_gpiolib_init(void) s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2, ARRAY_SIZE(s5p6450_gpio_rbank_4bit2)); } else { - for (; s5p6440_nr_chips > 0; s5p6440_nr_chips--, s5p6440_chips++) - s3c_gpiolib_add(s5p6440_chips); + samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit, + ARRAY_SIZE(s5p6440_gpio_2bit)); samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, ARRAY_SIZE(s5p6440_gpio_4bit)); From 5b1bab2e9ee619599ae78fed1a6e300db84adfcf Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 25 Nov 2010 14:21:48 +0900 Subject: [PATCH 4/7] ARM: S5P64X0: Rename GPIOlib file to gpiolib.c This patch renames S5P64X0 GPIOlib file according to other S5P SoCs. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/Makefile | 2 +- arch/arm/mach-s5p64x0/{gpio.c => gpiolib.c} | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/mach-s5p64x0/{gpio.c => gpiolib.c} (99%) diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index 835d51b328f..ae6bf6feba8 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile @@ -12,7 +12,7 @@ obj- := # Core support for S5P64X0 system -obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpio.o +obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpiolib.c similarity index 99% rename from arch/arm/mach-s5p64x0/gpio.c rename to arch/arm/mach-s5p64x0/gpiolib.c index 0670fcceed4..072668a37ad 100644 --- a/arch/arm/mach-s5p64x0/gpio.c +++ b/arch/arm/mach-s5p64x0/gpiolib.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s5p64x0/gpio.c +/* linux/arch/arm/mach-s5p64x0/gpiolib.c * * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. * http://www.samsung.com From 232d10061c05a7d6c1ef8a0754fd45656db93118 Mon Sep 17 00:00:00 2001 From: Atul Dahiya Date: Thu, 2 Dec 2010 13:36:12 +0900 Subject: [PATCH 5/7] ARM: S5P64X0: Add clock support for RTC This patch adds RTC clock for S5P6450. Signed-off-by: Atul Dahiya Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/clock-s5p6450.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 7dbf3c968f5..b9cd130596c 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -230,6 +230,12 @@ static struct clk init_clocks_disable[] = { .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 5), + }, { + .name = "rtc", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 6), }, { .name = "adc", .id = -1, From f85cbea94c81cda931642c5db34b780de417981d Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Fri, 3 Dec 2010 20:45:48 +0900 Subject: [PATCH 6/7] ARM: S5P64X0: Change GPIOlib initialization to core_initcall This patch changes the gpiolib initialization from arch_initcall to core_initcall will allow us to make use of gpio functions in smdk64x0_machine_init function. Signed-off-by: Abhilash Kesavan Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/gpiolib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c index 072668a37ad..e7fb3b004e7 100644 --- a/arch/arm/mach-s5p64x0/gpiolib.c +++ b/arch/arm/mach-s5p64x0/gpiolib.c @@ -508,4 +508,4 @@ static int __init s5p64x0_gpiolib_init(void) return 0; } -arch_initcall(s5p64x0_gpiolib_init); +core_initcall(s5p64x0_gpiolib_init); From 9af7d94f2966895b37b8ef1e0d88bd4d9e317e74 Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Wed, 22 Dec 2010 13:31:49 +0900 Subject: [PATCH 7/7] ARM: S5P6440: Change the name for MMC Special Clock Change the name of mmc spcial clock from mmc_bus to sclk_mmc to be in line with the naming across the S5P SoCs Signed-off-by: Abhilash Kesavan Signed-off-by: Sangbeom Kim [kgene.kim@samsung.com: minor edit of title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/clock-s5p6440.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index e4883dc1c8d..d27ff1a9f48 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 0, .ctrlbit = (1 << 24), .enable = s5p64x0_sclk_ctrl, @@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 1, .ctrlbit = (1 << 25), .enable = s5p64x0_sclk_ctrl, @@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 2, .ctrlbit = (1 << 26), .enable = s5p64x0_sclk_ctrl,