gma500: Add support for Intel GMBUS
Before we integrate the new SDVO code we need GMBUS support Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
9c8cee4713
commit
5c0c1d50d7
6 changed files with 588 additions and 0 deletions
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@ -11,6 +11,7 @@ gma500_gfx-y += gem_glue.o \
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gtt.o \
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intel_bios.o \
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intel_i2c.o \
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intel_gmbus.o \
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intel_opregion.o \
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mmu.o \
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power.o \
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493
drivers/gpu/drm/gma500/intel_gmbus.c
Normal file
493
drivers/gpu/drm/gma500/intel_gmbus.c
Normal file
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@ -0,0 +1,493 @@
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/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2008,2010 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include "drmP.h"
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#include "drm.h"
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#include "psb_intel_drv.h"
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#include "gma_drm.h"
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#include "psb_drv.h"
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#include "psb_intel_reg.h"
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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int ret__ = 0; \
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while (! (COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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/* Intel GPIO access functions */
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#define I2C_RISEFALL_TIME 20
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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struct intel_gpio {
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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struct drm_psb_private *dev_priv;
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u32 reg;
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};
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void
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gma_intel_i2c_reset(struct drm_device *dev)
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{
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REG_WRITE(GMBUS0, 0);
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}
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static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
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{
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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/* FIXME: We are never Pineview, right?
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u32 val;
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if (!IS_PINEVIEW(dev_priv->dev))
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return;
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val = REG_READ(DSPCLK_GATE_D);
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if (enable)
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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REG_WRITE(DSPCLK_GATE_D, val);
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return;
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*/
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}
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static u32 get_reserved(struct intel_gpio *gpio)
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{
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struct drm_psb_private *dev_priv = gpio->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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reserved = REG_READ(gpio->reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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return reserved;
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}
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static int get_clock(void *data)
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{
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struct intel_gpio *gpio = data;
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struct drm_psb_private *dev_priv = gpio->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = get_reserved(gpio);
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REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
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REG_WRITE(gpio->reg, reserved);
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return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_gpio *gpio = data;
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struct drm_psb_private *dev_priv = gpio->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = get_reserved(gpio);
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REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
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REG_WRITE(gpio->reg, reserved);
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return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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{
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struct intel_gpio *gpio = data;
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struct drm_psb_private *dev_priv = gpio->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = get_reserved(gpio);
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u32 clock_bits;
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if (state_high)
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clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
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else
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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REG_WRITE(gpio->reg, reserved | clock_bits);
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REG_READ(gpio->reg); /* Posting */
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}
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static void set_data(void *data, int state_high)
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{
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struct intel_gpio *gpio = data;
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struct drm_psb_private *dev_priv = gpio->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = get_reserved(gpio);
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u32 data_bits;
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if (state_high)
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data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
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else
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data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
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GPIO_DATA_VAL_MASK;
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REG_WRITE(gpio->reg, reserved | data_bits);
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REG_READ(gpio->reg);
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}
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static struct i2c_adapter *
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intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
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{
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static const int map_pin_to_reg[] = {
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0,
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GPIOB,
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GPIOA,
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GPIOC,
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GPIOD,
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GPIOE,
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0,
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GPIOF,
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};
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struct intel_gpio *gpio;
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if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
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return NULL;
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gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
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if (gpio == NULL)
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return NULL;
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gpio->reg = map_pin_to_reg[pin];
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gpio->dev_priv = dev_priv;
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snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
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"gma500 GPIO%c", "?BACDE?F"[pin]);
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gpio->adapter.owner = THIS_MODULE;
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gpio->adapter.algo_data = &gpio->algo;
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gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
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gpio->algo.setsda = set_data;
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gpio->algo.setscl = set_clock;
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gpio->algo.getsda = get_data;
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gpio->algo.getscl = get_clock;
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gpio->algo.udelay = I2C_RISEFALL_TIME;
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gpio->algo.timeout = usecs_to_jiffies(2200);
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gpio->algo.data = gpio;
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if (i2c_bit_add_bus(&gpio->adapter))
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goto out_free;
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return &gpio->adapter;
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out_free:
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kfree(gpio);
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return NULL;
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}
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static int
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intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
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struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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struct intel_gpio *gpio = container_of(adapter,
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struct intel_gpio,
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adapter);
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int ret;
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gma_intel_i2c_reset(dev_priv->dev);
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intel_i2c_quirk_set(dev_priv, true);
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set_data(gpio, 1);
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set_clock(gpio, 1);
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udelay(I2C_RISEFALL_TIME);
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ret = adapter->algo->master_xfer(adapter, msgs, num);
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set_data(gpio, 1);
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set_clock(gpio, 1);
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intel_i2c_quirk_set(dev_priv, false);
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return ret;
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}
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static int
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gmbus_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_psb_private *dev_priv = adapter->algo_data;
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struct drm_device *dev = dev_priv->dev;
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int i, reg_offset;
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if (bus->force_bit)
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return intel_i2c_quirk_xfer(dev_priv,
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bus->force_bit, msgs, num);
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reg_offset = 0;
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REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
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for (i = 0; i < num; i++) {
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u16 len = msgs[i].len;
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u8 *buf = msgs[i].buf;
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if (msgs[i].flags & I2C_M_RD) {
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REG_WRITE(GMBUS1 + reg_offset,
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GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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REG_READ(GMBUS2+reg_offset);
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do {
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u32 val, loop = 0;
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if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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val = REG_READ(GMBUS3 + reg_offset);
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do {
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*buf++ = val & 0xff;
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val >>= 8;
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} while (--len && ++loop < 4);
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} while (len);
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} else {
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u32 val, loop;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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REG_WRITE(GMBUS3 + reg_offset, val);
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REG_WRITE(GMBUS1 + reg_offset,
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(i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
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(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
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(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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REG_READ(GMBUS2+reg_offset);
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while (len) {
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if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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REG_WRITE(GMBUS3 + reg_offset, val);
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REG_READ(GMBUS2+reg_offset);
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}
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}
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if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
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goto timeout;
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if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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}
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goto done;
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clear_err:
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/* Toggle the Software Clear Interrupt bit. This has the effect
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* of resetting the GMBUS controller and so clearing the
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* BUS_ERROR raised by the slave's NAK.
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*/
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REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
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REG_WRITE(GMBUS1 + reg_offset, 0);
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done:
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/* Mark the GMBUS interface as disabled. We will re-enable it at the
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* start of the next xfer, till then let it sleep.
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*/
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REG_WRITE(GMBUS0 + reg_offset, 0);
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return i;
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timeout:
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DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
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bus->reg0 & 0xff, bus->adapter.name);
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REG_WRITE(GMBUS0 + reg_offset, 0);
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/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
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bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
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if (!bus->force_bit)
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return -ENOMEM;
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return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
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}
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static u32 gmbus_func(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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if (bus->force_bit)
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bus->force_bit->algo->functionality(bus->force_bit);
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return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
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/* I2C_FUNC_10BIT_ADDR | */
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I2C_FUNC_SMBUS_READ_BLOCK_DATA |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
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}
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static const struct i2c_algorithm gmbus_algorithm = {
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.master_xfer = gmbus_xfer,
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.functionality = gmbus_func
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};
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/**
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* intel_gmbus_setup - instantiate all Intel i2c GMBuses
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* @dev: DRM device
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*/
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int gma_intel_setup_gmbus(struct drm_device *dev)
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{
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static const char *names[GMBUS_NUM_PORTS] = {
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"disabled",
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"ssc",
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"vga",
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"panel",
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"dpc",
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"dpb",
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"reserved",
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"dpd",
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};
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struct drm_psb_private *dev_priv = dev->dev_private;
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int ret, i;
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dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
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GFP_KERNEL);
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if (dev_priv->gmbus == NULL)
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return -ENOMEM;
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for (i = 0; i < GMBUS_NUM_PORTS; i++) {
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struct intel_gmbus *bus = &dev_priv->gmbus[i];
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bus->adapter.owner = THIS_MODULE;
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bus->adapter.class = I2C_CLASS_DDC;
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snprintf(bus->adapter.name,
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sizeof(bus->adapter.name),
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"gma500 gmbus %s",
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names[i]);
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bus->adapter.dev.parent = &dev->pdev->dev;
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bus->adapter.algo_data = dev_priv;
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bus->adapter.algo = &gmbus_algorithm;
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ret = i2c_add_adapter(&bus->adapter);
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if (ret)
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goto err;
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/* By default use a conservative clock rate */
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bus->reg0 = i | GMBUS_RATE_100KHZ;
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/* XXX force bit banging until GMBUS is fully debugged */
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bus->force_bit = intel_gpio_create(dev_priv, i);
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}
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gma_intel_i2c_reset(dev_priv->dev);
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return 0;
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err:
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while (--i) {
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struct intel_gmbus *bus = &dev_priv->gmbus[i];
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i2c_del_adapter(&bus->adapter);
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}
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kfree(dev_priv->gmbus);
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dev_priv->gmbus = NULL;
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return ret;
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}
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void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
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/* speed:
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* 0x0 = 100 KHz
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* 0x1 = 50 KHz
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* 0x2 = 400 KHz
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* 0x3 = 1000 Khz
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*/
|
||||
bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
|
||||
}
|
||||
|
||||
void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
||||
{
|
||||
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
||||
|
||||
if (force_bit) {
|
||||
if (bus->force_bit == NULL) {
|
||||
struct drm_psb_private *dev_priv = adapter->algo_data;
|
||||
bus->force_bit = intel_gpio_create(dev_priv,
|
||||
bus->reg0 & 0xff);
|
||||
}
|
||||
} else {
|
||||
if (bus->force_bit) {
|
||||
i2c_del_adapter(bus->force_bit);
|
||||
kfree(bus->force_bit);
|
||||
bus->force_bit = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gma_intel_teardown_gmbus(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int i;
|
||||
|
||||
if (dev_priv->gmbus == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < GMBUS_NUM_PORTS; i++) {
|
||||
struct intel_gmbus *bus = &dev_priv->gmbus[i];
|
||||
if (bus->force_bit) {
|
||||
i2c_del_adapter(bus->force_bit);
|
||||
kfree(bus->force_bit);
|
||||
}
|
||||
i2c_del_adapter(&bus->adapter);
|
||||
}
|
||||
|
||||
kfree(dev_priv->gmbus);
|
||||
dev_priv->gmbus = NULL;
|
||||
}
|
|
@ -290,11 +290,17 @@ static void psb_get_core_freq(struct drm_device *dev)
|
|||
static int psb_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
psb_get_core_freq(dev);
|
||||
gma_intel_setup_gmbus(dev);
|
||||
gma_intel_opregion_init(dev);
|
||||
psb_intel_init_bios(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void psb_chip_teardown(struct drm_device *dev)
|
||||
{
|
||||
gma_intel_teardown_gmbus(dev);
|
||||
}
|
||||
|
||||
const struct psb_ops psb_chip_ops = {
|
||||
.name = "Poulsbo",
|
||||
.accel_2d = 1,
|
||||
|
@ -302,6 +308,7 @@ const struct psb_ops psb_chip_ops = {
|
|||
.crtcs = 2,
|
||||
.sgx_offset = PSB_SGX_OFFSET,
|
||||
.chip_setup = psb_chip_setup,
|
||||
.chip_teardown = psb_chip_teardown,
|
||||
|
||||
.crtc_helper = &psb_intel_helper_funcs,
|
||||
.crtc_funcs = &psb_intel_crtc_funcs,
|
||||
|
|
|
@ -260,6 +260,12 @@ struct psb_intel_opregion {
|
|||
int enabled;
|
||||
};
|
||||
|
||||
struct intel_gmbus {
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_adapter *force_bit;
|
||||
u32 reg0;
|
||||
};
|
||||
|
||||
struct psb_ops;
|
||||
|
||||
#define PSB_NUM_PIPE 3
|
||||
|
@ -336,6 +342,9 @@ struct drm_psb_private {
|
|||
/* PCI revision ID for B0:D2:F0 */
|
||||
uint8_t platform_rev_id;
|
||||
|
||||
/* gmbus */
|
||||
struct intel_gmbus *gmbus;
|
||||
|
||||
/*
|
||||
* LVDS info
|
||||
*/
|
||||
|
|
|
@ -235,5 +235,11 @@ extern int psb_intel_lvds_set_property(struct drm_connector *connector,
|
|||
extern void psb_intel_lvds_destroy(struct drm_connector *connector);
|
||||
extern const struct drm_encoder_funcs psb_intel_lvds_enc_funcs;
|
||||
|
||||
/* intel_gmbus.c */
|
||||
extern void gma_intel_i2c_reset(struct drm_device *dev);
|
||||
extern int gma_intel_setup_gmbus(struct drm_device *dev);
|
||||
extern void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
|
||||
extern void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
|
||||
extern void gma_intel_teardown_gmbus(struct drm_device *dev);
|
||||
|
||||
#endif /* __INTEL_DRV_H__ */
|
||||
|
|
|
@ -17,6 +17,78 @@
|
|||
#ifndef __PSB_INTEL_REG_H__
|
||||
#define __PSB_INTEL_REG_H__
|
||||
|
||||
/*
|
||||
* GPIO regs
|
||||
*/
|
||||
#define GPIOA 0x5010
|
||||
#define GPIOB 0x5014
|
||||
#define GPIOC 0x5018
|
||||
#define GPIOD 0x501c
|
||||
#define GPIOE 0x5020
|
||||
#define GPIOF 0x5024
|
||||
#define GPIOG 0x5028
|
||||
#define GPIOH 0x502c
|
||||
# define GPIO_CLOCK_DIR_MASK (1 << 0)
|
||||
# define GPIO_CLOCK_DIR_IN (0 << 1)
|
||||
# define GPIO_CLOCK_DIR_OUT (1 << 1)
|
||||
# define GPIO_CLOCK_VAL_MASK (1 << 2)
|
||||
# define GPIO_CLOCK_VAL_OUT (1 << 3)
|
||||
# define GPIO_CLOCK_VAL_IN (1 << 4)
|
||||
# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
|
||||
# define GPIO_DATA_DIR_MASK (1 << 8)
|
||||
# define GPIO_DATA_DIR_IN (0 << 9)
|
||||
# define GPIO_DATA_DIR_OUT (1 << 9)
|
||||
# define GPIO_DATA_VAL_MASK (1 << 10)
|
||||
# define GPIO_DATA_VAL_OUT (1 << 11)
|
||||
# define GPIO_DATA_VAL_IN (1 << 12)
|
||||
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
|
||||
|
||||
#define GMBUS0 0x5100 /* clock/port select */
|
||||
#define GMBUS_RATE_100KHZ (0<<8)
|
||||
#define GMBUS_RATE_50KHZ (1<<8)
|
||||
#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
|
||||
#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
|
||||
#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
|
||||
#define GMBUS_PORT_DISABLED 0
|
||||
#define GMBUS_PORT_SSC 1
|
||||
#define GMBUS_PORT_VGADDC 2
|
||||
#define GMBUS_PORT_PANEL 3
|
||||
#define GMBUS_PORT_DPC 4 /* HDMIC */
|
||||
#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
|
||||
/* 6 reserved */
|
||||
#define GMBUS_PORT_DPD 7 /* HDMID */
|
||||
#define GMBUS_NUM_PORTS 8
|
||||
#define GMBUS1 0x5104 /* command/status */
|
||||
#define GMBUS_SW_CLR_INT (1<<31)
|
||||
#define GMBUS_SW_RDY (1<<30)
|
||||
#define GMBUS_ENT (1<<29) /* enable timeout */
|
||||
#define GMBUS_CYCLE_NONE (0<<25)
|
||||
#define GMBUS_CYCLE_WAIT (1<<25)
|
||||
#define GMBUS_CYCLE_INDEX (2<<25)
|
||||
#define GMBUS_CYCLE_STOP (4<<25)
|
||||
#define GMBUS_BYTE_COUNT_SHIFT 16
|
||||
#define GMBUS_SLAVE_INDEX_SHIFT 8
|
||||
#define GMBUS_SLAVE_ADDR_SHIFT 1
|
||||
#define GMBUS_SLAVE_READ (1<<0)
|
||||
#define GMBUS_SLAVE_WRITE (0<<0)
|
||||
#define GMBUS2 0x5108 /* status */
|
||||
#define GMBUS_INUSE (1<<15)
|
||||
#define GMBUS_HW_WAIT_PHASE (1<<14)
|
||||
#define GMBUS_STALL_TIMEOUT (1<<13)
|
||||
#define GMBUS_INT (1<<12)
|
||||
#define GMBUS_HW_RDY (1<<11)
|
||||
#define GMBUS_SATOER (1<<10)
|
||||
#define GMBUS_ACTIVE (1<<9)
|
||||
#define GMBUS3 0x510c /* data buffer bytes 3-0 */
|
||||
#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
|
||||
#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
|
||||
#define GMBUS_NAK_EN (1<<3)
|
||||
#define GMBUS_IDLE_EN (1<<2)
|
||||
#define GMBUS_HW_WAIT_EN (1<<1)
|
||||
#define GMBUS_HW_RDY_EN (1<<0)
|
||||
#define GMBUS5 0x5120 /* byte index */
|
||||
#define GMBUS_2BYTE_INDEX_EN (1<<31)
|
||||
|
||||
#define BLC_PWM_CTL 0x61254
|
||||
#define BLC_PWM_CTL2 0x61250
|
||||
#define BLC_PWM_CTL_C 0x62254
|
||||
|
|
Reference in a new issue