[SPARC]: Make SBUS dma code similar to EBUS
From: Georg Chini <georg.chini@triaton-webhosting.com> Introduce some sbus_dma routines similar to the ebus_dma stuff to make the code look nearly the same for both cases. Thanks to Christopher for testing. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Georg Chini
David S. Miller
parent
ee1858d312
commit
5a820fa7e1
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@ -61,6 +61,14 @@ MODULE_DESCRIPTION("Sun CS4231");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
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#ifdef SBUS_SUPPORT
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struct sbus_dma_info {
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spinlock_t lock;
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int dir;
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void __iomem *regs;
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};
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#endif
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typedef struct snd_cs4231 {
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spinlock_t lock;
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void __iomem *port;
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@ -69,6 +77,11 @@ typedef struct snd_cs4231 {
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struct ebus_dma_info eb2p;
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#endif
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#ifdef SBUS_SUPPORT
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struct sbus_dma_info sb2c;
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struct sbus_dma_info sb2p;
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#endif
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u32 flags;
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#define CS4231_FLAG_EBUS 0x00000001
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#define CS4231_FLAG_PLAYBACK 0x00000002
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@ -251,6 +264,15 @@ static cs4231_t *cs4231_list;
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#define APCPNVA 0x38UL /* APC Play DMA Next Address */
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#define APCPNC 0x3cUL /* APC Play Next Count */
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/* Defines for SBUS DMA-routines */
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#define APCVA 0x0UL /* APC DMA Address */
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#define APCC 0x4UL /* APC Count */
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#define APCNVA 0x8UL /* APC DMA Next Address */
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#define APCNC 0xcUL /* APC Next Count */
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#define APC_PLAY 0x30UL /* Play registers start at 0x30 */
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#define APC_RECORD 0x20UL /* Record registers start at 0x20 */
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/* APCCSR bits */
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#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
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@ -471,6 +493,103 @@ static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
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return ret;
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}
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/*
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* SBUS DMA routines
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*/
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#ifdef SBUS_SUPPORT
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int sbus_dma_request(struct sbus_dma_info *base, dma_addr_t bus_addr, size_t len)
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{
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unsigned long flags;
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u32 test, csr;
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int err;
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if (len >= (1 << 24))
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return -EINVAL;
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spin_lock_irqsave(&base->lock, flags);
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csr = sbus_readl(base->regs + APCCSR);
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err = -EINVAL;
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test = APC_CDMA_READY;
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if ( base->dir == APC_PLAY )
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test = APC_PDMA_READY;
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if (!(csr & test))
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goto out;
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err = -EBUSY;
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csr = sbus_readl(base->regs + APCCSR);
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test = APC_XINT_CNVA;
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if ( base->dir == APC_PLAY )
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test = APC_XINT_PNVA;
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if (!(csr & test))
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goto out;
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err = 0;
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sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
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sbus_writel(len, base->regs + base->dir + APCNC);
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out:
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spin_unlock_irqrestore(&base->lock, flags);
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return err;
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}
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void sbus_dma_prepare(struct sbus_dma_info *base)
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{
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unsigned long flags;
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u32 csr, test;
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spin_lock_irqsave(&base->lock, flags);
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csr = sbus_readl(base->regs + APCCSR);
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test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
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APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
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APC_XINT_PENA;
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if ( base->dir == APC_RECORD )
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test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
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APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
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csr |= test;
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sbus_writel(csr, base->regs + APCCSR);
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spin_unlock_irqrestore(&base->lock, flags);
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}
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void sbus_dma_enable(struct sbus_dma_info *base, int on)
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{
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unsigned long flags;
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u32 csr, shift;
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spin_lock_irqsave(&base->lock, flags);
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if (!on) {
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if (base->dir == APC_PLAY) {
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sbus_writel(0, base->regs + base->dir + APCNVA);
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sbus_writel(1, base->regs + base->dir + APCC);
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}
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else
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{
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sbus_writel(0, base->regs + base->dir + APCNC);
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sbus_writel(0, base->regs + base->dir + APCVA);
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}
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}
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udelay(500);
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csr = sbus_readl(base->regs + APCCSR);
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shift = 0;
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if ( base->dir == APC_PLAY )
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shift = 1;
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if (on)
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csr &= ~(APC_CPAUSE << shift);
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else
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csr |= (APC_CPAUSE << shift);
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sbus_writel(csr, base->regs + APCCSR);
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if (on)
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csr |= (APC_CDMA_READY << shift);
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else
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csr &= ~(APC_CDMA_READY << shift);
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sbus_writel(csr, base->regs + APCCSR);
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spin_unlock_irqrestore(&base->lock, flags);
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}
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unsigned int sbus_dma_addr(struct sbus_dma_info *base)
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{
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return sbus_readl(base->regs + base->dir + APCVA);
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}
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#endif
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/*
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* CS4231 detection / MCE routines
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*/
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@ -589,29 +708,21 @@ static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info *p, snd_pcm_substre
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#endif
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#ifdef SBUS_SUPPORT
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static void snd_cs4231_sbus_advance_dma(snd_pcm_substream_t *substream, unsigned int *periods_sent)
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static void snd_cs4231_sbus_advance_dma(struct sbus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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snd_pcm_runtime_t *runtime = substream->runtime;
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unsigned int period_size = snd_pcm_lib_period_bytes(substream);
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unsigned int offset = period_size * (*periods_sent % runtime->periods);
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while (1) {
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unsigned int period_size = snd_pcm_lib_period_bytes(substream);
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unsigned int offset = period_size * (*periods_sent);
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if (runtime->period_size > 0xffff + 1)
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BUG();
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switch (substream->stream) {
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case SNDRV_PCM_STREAM_PLAYBACK:
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sbus_writel(runtime->dma_addr + offset, chip->port + APCPNVA);
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sbus_writel(period_size, chip->port + APCPNC);
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break;
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case SNDRV_PCM_STREAM_CAPTURE:
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sbus_writel(runtime->dma_addr + offset, chip->port + APCCNVA);
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sbus_writel(period_size, chip->port + APCCNC);
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break;
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}
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(*periods_sent) = (*periods_sent + 1) % runtime->periods;
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if (period_size > 0xffff + 1)
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BUG();
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if (sbus_dma_request(p, runtime->dma_addr + offset, period_size))
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return;
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(*periods_sent) = (*periods_sent + 1) % runtime->periods;
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}
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}
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#endif
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@ -646,59 +757,27 @@ static void cs4231_dma_trigger(snd_pcm_substream_t *substream, unsigned int what
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} else {
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#endif
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#ifdef SBUS_SUPPORT
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u32 csr = sbus_readl(chip->port + APCCSR);
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/* I don't know why, but on sbus the period counter must
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* only start counting after the first period is sent.
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* Therefore this dummy thing.
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*/
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unsigned int dummy = 0;
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switch (what) {
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case CS4231_PLAYBACK_ENABLE:
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if (what & CS4231_PLAYBACK_ENABLE) {
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if (on) {
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csr &= ~APC_XINT_PLAY;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_PPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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snd_cs4231_sbus_advance_dma(substream, &dummy);
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csr |= APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
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APC_XINT_PLAY | APC_XINT_EMPT | APC_XINT_GENL |
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APC_XINT_PENA | APC_PDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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sbus_dma_prepare(&chip->sb2p);
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sbus_dma_enable(&chip->sb2p, 1);
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snd_cs4231_sbus_advance_dma(&chip->sb2p,
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chip->playback_substream,
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&chip->p_periods_sent);
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} else {
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csr |= APC_PPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_PDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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sbus_dma_enable(&chip->sb2p, 0);
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}
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break;
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case CS4231_RECORD_ENABLE:
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}
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if (what & CS4231_RECORD_ENABLE) {
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if (on) {
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csr &= ~APC_XINT_CAPT;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_CPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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snd_cs4231_sbus_advance_dma(substream, &dummy);
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csr |= APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
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APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL |
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APC_CDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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sbus_dma_prepare(&chip->sb2c);
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sbus_dma_enable(&chip->sb2c, 1);
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snd_cs4231_sbus_advance_dma(&chip->sb2c,
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chip->capture_substream,
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&chip->c_periods_sent);
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} else {
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csr |= APC_CPAUSE;
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sbus_writel(csr, chip->port + APCCSR);
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csr &= ~APC_CDMA_READY;
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sbus_writel(csr, chip->port + APCCSR);
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sbus_dma_enable(&chip->sb2c, 0);
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}
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break;
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}
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#endif
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#ifdef EBUS_SUPPORT
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@ -1136,10 +1215,7 @@ static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
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if (runtime->period_size > 0xffff + 1)
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BUG();
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snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (runtime->period_size - 1) & 0x00ff);
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snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (runtime->period_size - 1) >> 8 & 0x00ff);
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chip->p_periods_sent = 0;
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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@ -1171,16 +1247,14 @@ static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
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static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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snd_pcm_runtime_t *runtime = substream->runtime;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
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CS4231_RECORD_PIO);
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snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (runtime->period_size - 1) & 0x00ff);
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snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (runtime->period_size - 1) >> 8 & 0x00ff);
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chip->c_periods_sent = 0;
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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@ -1199,15 +1273,41 @@ static void snd_cs4231_overrange(cs4231_t *chip)
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chip->capture_substream->runtime->overrange++;
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}
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static irqreturn_t snd_cs4231_generic_interrupt(cs4231_t *chip)
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#ifdef SBUS_SUPPORT
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static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned long flags;
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unsigned char status;
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u32 csr;
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cs4231_t *chip = dev_id;
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/*This is IRQ is not raised by the cs4231*/
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if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
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return IRQ_NONE;
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/* ACK the APC interrupt. */
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csr = sbus_readl(chip->port + APCCSR);
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sbus_writel(csr, chip->port + APCCSR);
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if ((chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) &&
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(csr & APC_PLAY_INT) &&
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(csr & APC_XINT_PNVA) &&
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!(csr & APC_XINT_EMPT)) {
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snd_pcm_period_elapsed(chip->playback_substream);
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snd_cs4231_sbus_advance_dma(&chip->sb2p, chip->playback_substream,
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&chip->p_periods_sent);
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}
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if ((chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) &&
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(csr & APC_CAPT_INT) &&
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(csr & APC_XINT_CNVA) &&
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!(csr & APC_XINT_EMPT)) {
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snd_pcm_period_elapsed(chip->capture_substream);
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snd_cs4231_sbus_advance_dma(&chip->sb2c,chip->capture_substream,
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&chip->c_periods_sent);
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}
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status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
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if (status & CS4231_TIMER_IRQ) {
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@ -1225,36 +1325,6 @@ static irqreturn_t snd_cs4231_generic_interrupt(cs4231_t *chip)
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return 0;
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}
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#ifdef SBUS_SUPPORT
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static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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cs4231_t *chip = dev_id;
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/* ACK the APC interrupt. */
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u32 csr = sbus_readl(chip->port + APCCSR);
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sbus_writel(csr, chip->port + APCCSR);
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if ((chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) &&
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(csr & APC_PLAY_INT) &&
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(csr & APC_XINT_PNVA) &&
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!(csr & APC_XINT_EMPT)) {
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snd_cs4231_sbus_advance_dma(chip->playback_substream,
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&chip->p_periods_sent);
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snd_pcm_period_elapsed(chip->playback_substream);
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}
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if ((chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) &&
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(csr & APC_CAPT_INT) &&
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(csr & APC_XINT_CNVA)) {
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snd_cs4231_sbus_advance_dma(chip->capture_substream,
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&chip->c_periods_sent);
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snd_pcm_period_elapsed(chip->capture_substream);
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}
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return snd_cs4231_generic_interrupt(chip);
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}
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#endif
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#ifdef EBUS_SUPPORT
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@ -1284,24 +1354,29 @@ static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event,
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static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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size_t ptr, residue, period_bytes;
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size_t ptr;
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#ifdef EBUS_SUPPORT
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size_t residue, period_bytes;
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#endif
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if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
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return 0;
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#ifdef EBUS_SUPPORT
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period_bytes = snd_pcm_lib_period_bytes(substream);
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ptr = period_bytes * chip->p_periods_sent;
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#ifdef EBUS_SUPPORT
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if (chip->flags & CS4231_FLAG_EBUS) {
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residue = ebus_dma_residue(&chip->eb2p);
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ptr += period_bytes - residue;
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} else {
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#endif
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#ifdef SBUS_SUPPORT
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residue = sbus_readl(chip->port + APCPC);
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ptr = sbus_dma_addr(&chip->sb2p);
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if (ptr != 0)
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ptr -= substream->runtime->dma_addr;
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#endif
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#ifdef EBUS_SUPPORT
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}
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#endif
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ptr += period_bytes - residue;
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return bytes_to_frames(substream->runtime, ptr);
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}
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@ -1309,24 +1384,29 @@ static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substr
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static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
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{
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cs4231_t *chip = snd_pcm_substream_chip(substream);
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size_t ptr, residue, period_bytes;
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size_t ptr;
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#ifdef EBUS_SUPPORT
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size_t residue, period_bytes;
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#endif
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if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
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return 0;
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#ifdef EBUS_SUPPORT
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period_bytes = snd_pcm_lib_period_bytes(substream);
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ptr = period_bytes * chip->c_periods_sent;
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#ifdef EBUS_SUPPORT
|
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if (chip->flags & CS4231_FLAG_EBUS) {
|
||||
residue = ebus_dma_residue(&chip->eb2c);
|
||||
ptr += period_bytes - residue;
|
||||
} else {
|
||||
#endif
|
||||
#ifdef SBUS_SUPPORT
|
||||
residue = sbus_readl(chip->port + APCCC);
|
||||
ptr = sbus_dma_addr(&chip->sb2c);
|
||||
if (ptr != 0)
|
||||
ptr -= substream->runtime->dma_addr;
|
||||
#endif
|
||||
#ifdef EBUS_SUPPORT
|
||||
}
|
||||
#endif
|
||||
ptr += period_bytes - residue;
|
||||
return bytes_to_frames(substream->runtime, ptr);
|
||||
}
|
||||
|
||||
|
|
@ -1983,6 +2063,8 @@ static int __init snd_cs4231_sbus_create(snd_card_t *card,
|
|||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
spin_lock_init(&chip->sb2c.lock);
|
||||
spin_lock_init(&chip->sb2p.lock);
|
||||
init_MUTEX(&chip->mce_mutex);
|
||||
init_MUTEX(&chip->open_mutex);
|
||||
chip->card = card;
|
||||
|
|
@ -1998,6 +2080,11 @@ static int __init snd_cs4231_sbus_create(snd_card_t *card,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
chip->sb2c.regs = chip->port;
|
||||
chip->sb2p.regs = chip->port;
|
||||
chip->sb2c.dir = APC_RECORD;
|
||||
chip->sb2p.dir = APC_PLAY;
|
||||
|
||||
if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
|
||||
SA_SHIRQ, "cs4231", chip)) {
|
||||
snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
|
||||
|
|
|
|||
Reference in New Issue