MIPS: pci: convert lantiq driver to OF
Implement support for OF inside the lantiq PCI driver. The patch also splits pcibios_plat_dev_init and pcibios_map_irq out into their own file to accomodate coexistance with the upcoming pcie driver. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3806/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
ddd4eeca96
commit
57c8cb8f24
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@ -18,7 +18,6 @@ config SOC_XWAY
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select HW_HAS_PCI
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endchoice
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choice
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prompt "Devicetree"
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@ -27,4 +26,8 @@ config DT_EASY50712
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depends on SOC_XWAY
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endchoice
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config PCI_LANTIQ
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bool "PCI Support"
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depends on SOC_XWAY && PCI
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endif
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@ -41,7 +41,8 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
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obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
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obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
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obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
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obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
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obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
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@ -0,0 +1,40 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;
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int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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if (ltq_pci_plat_arch_init)
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return ltq_pci_plat_arch_init(dev);
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if (ltq_pci_plat_dev_init)
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return ltq_pci_plat_dev_init(dev);
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return 0;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct of_irq dev_irq;
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int irq;
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if (of_irq_map_pci(dev, &dev_irq)) {
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dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n",
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slot, pin);
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return 0;
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}
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irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier,
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dev_irq.size);
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dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq);
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return irq;
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}
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@ -13,8 +13,12 @@
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <asm/pci.h>
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#include <asm/gpio.h>
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@ -22,17 +26,9 @@
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#include <lantiq_soc.h>
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#include <lantiq_irq.h>
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#include <lantiq_platform.h>
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#include "pci-lantiq.h"
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#define LTQ_PCI_CFG_BASE 0x17000000
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#define LTQ_PCI_CFG_SIZE 0x00008000
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#define LTQ_PCI_MEM_BASE 0x18000000
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#define LTQ_PCI_MEM_SIZE 0x02000000
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#define LTQ_PCI_IO_BASE 0x1AE00000
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#define LTQ_PCI_IO_SIZE 0x00200000
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#define PCI_CR_FCI_ADDR_MAP0 0x00C0
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#define PCI_CR_FCI_ADDR_MAP1 0x00C4
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#define PCI_CR_FCI_ADDR_MAP2 0x00C8
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@ -71,50 +67,24 @@
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__iomem void *ltq_pci_mapped_cfg;
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static __iomem void *ltq_pci_membase;
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int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
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/* Since the PCI REQ pins can be reused for other functionality, make it
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possible to exclude those from interpretation by the PCI controller */
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static int ltq_pci_req_mask = 0xf;
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static int *ltq_pci_irq_map;
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struct pci_ops ltq_pci_ops = {
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static int reset_gpio;
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static struct clk *clk_pci, *clk_external;
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static struct resource pci_io_resource;
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static struct resource pci_mem_resource;
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static struct pci_ops pci_ops = {
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.read = ltq_pci_read_config_dword,
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.write = ltq_pci_write_config_dword
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};
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static struct resource pci_io_resource = {
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.name = "pci io space",
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.start = LTQ_PCI_IO_BASE,
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.end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.name = "pci memory space",
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.start = LTQ_PCI_MEM_BASE,
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.end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ltq_pci_controller = {
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.pci_ops = <q_pci_ops,
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static struct pci_controller pci_controller = {
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.pci_ops = &pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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if (ltqpci_plat_dev_init)
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return ltqpci_plat_dev_init(dev);
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return 0;
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}
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static u32 ltq_calc_bar11mask(void)
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static inline u32 ltq_calc_bar11mask(void)
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{
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u32 mem, bar11mask;
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@ -125,32 +95,42 @@ static u32 ltq_calc_bar11mask(void)
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return bar11mask;
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}
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static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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static int __devinit ltq_pci_startup(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const __be32 *req_mask, *bus_clk;
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u32 temp_buffer;
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/* set clock to 33Mhz */
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if (ltq_is_ar9()) {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
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} else {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
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/* get our clocks */
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clk_pci = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk_pci)) {
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dev_err(&pdev->dev, "failed to get pci clock\n");
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return PTR_ERR(clk_pci);
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}
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/* external or internal clock ? */
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if (conf->clock) {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
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LTQ_CGU_IFCCR);
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ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
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} else {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
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LTQ_CGU_IFCCR);
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ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
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clk_external = clk_get(&pdev->dev, "external");
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if (IS_ERR(clk_external)) {
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clk_put(clk_pci);
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dev_err(&pdev->dev, "failed to get external pci clock\n");
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return PTR_ERR(clk_external);
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}
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/* setup pci clock and gpis used by pci */
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gpio_request(21, "pci-reset");
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/* read the bus speed that we want */
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bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
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if (bus_clk)
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clk_set_rate(clk_pci, *bus_clk);
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/* and enable the clocks */
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clk_enable(clk_pci);
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if (of_find_property(node, "lantiq,external-clock", NULL))
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clk_enable(clk_external);
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else
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clk_disable(clk_external);
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/* setup reset gpio used by pci */
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reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
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if (reset_gpio > 0)
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devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset");
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/* enable auto-switching between PCI and EBU */
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ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
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@ -163,7 +143,12 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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/* enable external 2 PCI masters */
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temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
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temp_buffer &= (~(ltq_pci_req_mask << 16));
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/* setup the request mask */
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req_mask = of_get_property(node, "req-mask", NULL);
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if (req_mask)
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temp_buffer &= ~((*req_mask & 0xf) << 16);
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else
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temp_buffer &= ~0xf0000;
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/* enable internal arbiter */
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temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
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/* enable internal PCI master reqest */
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@ -207,47 +192,55 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
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/* toggle reset pin */
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__gpio_set_value(21, 0);
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wmb();
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mdelay(1);
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__gpio_set_value(21, 1);
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return 0;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (ltq_pci_irq_map[slot])
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return ltq_pci_irq_map[slot];
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printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
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slot);
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if (reset_gpio > 0) {
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__gpio_set_value(reset_gpio, 0);
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wmb();
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mdelay(1);
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__gpio_set_value(reset_gpio, 1);
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}
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return 0;
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}
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static int __devinit ltq_pci_probe(struct platform_device *pdev)
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{
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struct ltq_pci_data *ltq_pci_data =
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(struct ltq_pci_data *) pdev->dev.platform_data;
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struct resource *res_cfg, *res_bridge;
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pci_clear_flags(PCI_PROBE_ONLY);
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ltq_pci_irq_map = ltq_pci_data->irq;
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ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
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ltq_pci_mapped_cfg =
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ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
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ltq_pci_controller.io_map_base =
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(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
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ltq_pci_startup(ltq_pci_data);
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register_pci_controller(<q_pci_controller);
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res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_cfg || !res_bridge) {
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dev_err(&pdev->dev, "missing memory reources\n");
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return -EINVAL;
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}
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ltq_pci_membase = devm_request_and_ioremap(&pdev->dev, res_bridge);
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ltq_pci_mapped_cfg = devm_request_and_ioremap(&pdev->dev, res_cfg);
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if (!ltq_pci_membase || !ltq_pci_mapped_cfg) {
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dev_err(&pdev->dev, "failed to remap resources\n");
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return -ENOMEM;
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}
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ltq_pci_startup(pdev);
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pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
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register_pci_controller(&pci_controller);
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return 0;
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}
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static struct platform_driver
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ltq_pci_driver = {
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static const struct of_device_id ltq_pci_match[] = {
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{ .compatible = "lantiq,pci-xway" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ltq_pci_match);
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static struct platform_driver ltq_pci_driver = {
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.probe = ltq_pci_probe,
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.driver = {
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.name = "ltq_pci",
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.name = "pci-xway",
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.owner = THIS_MODULE,
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.of_match_table = ltq_pci_match,
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},
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};
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@ -255,7 +248,7 @@ int __init pcibios_init(void)
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{
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int ret = platform_driver_register(<q_pci_driver);
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if (ret)
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printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
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pr_info("pci-xway: Error registering platform driver!");
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return ret;
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}
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