[libata] Address some checkpatch-spotted issues
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Jeff Garzik
parent
b447916e2b
commit
5796d1c4c8
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@ -74,8 +74,7 @@ static int pcmcia_set_mode(struct ata_link *link, struct ata_device **r_failed_d
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return ata_do_set_mode(link, r_failed_dev);
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if (memcmp(master->id + ATA_ID_FW_REV, slave->id + ATA_ID_FW_REV,
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ATA_ID_FW_REV_LEN + ATA_ID_PROD_LEN) == 0)
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{
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ATA_ID_FW_REV_LEN + ATA_ID_PROD_LEN) == 0) {
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/* Suspicious match, but could be two cards from
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the same vendor - check serial */
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if (memcmp(master->id + ATA_ID_SERNO, slave->id + ATA_ID_SERNO,
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@ -248,7 +247,8 @@ static int pcmcia_init_one(struct pcmcia_device *pdev)
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goto next_entry;
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io_base = pdev->io.BasePort1;
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ctl_base = pdev->io.BasePort1 + 0x0e;
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} else goto next_entry;
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} else
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goto next_entry;
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/* If we've got this far, we're done */
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break;
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}
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@ -285,8 +285,8 @@ next_entry:
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printk(KERN_WARNING DRV_NAME ": second channel not yet supported.\n");
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/*
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* Having done the PCMCIA plumbing the ATA side is relatively
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* sane.
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* Having done the PCMCIA plumbing the ATA side is relatively
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* sane.
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*/
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ret = -ENOMEM;
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host = ata_host_alloc(&pdev->dev, 1);
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@ -363,7 +363,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
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PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */
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PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d),
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PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */
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PCMCIA_DEVICE_MANF_CARD(0x0319, 0x0000), /* Hitachi */
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PCMCIA_DEVICE_MANF_CARD(0x0319, 0x0000), /* Hitachi */
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PCMCIA_DEVICE_MANF_CARD(0x2080, 0x0001),
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PCMCIA_DEVICE_MANF_CARD(0x4e01, 0x0100), /* Viking CFA */
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PCMCIA_DEVICE_MANF_CARD(0x4e01, 0x0200), /* Lexar, Viking CFA */
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@ -47,10 +47,10 @@
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#define DRV_VERSION "1.0"
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/* macro to calculate base address for ATA regs */
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#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
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#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
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/* macro to calculate base address for ADMA regs */
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#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
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#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
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/* macro to obtain addresses from ata_port */
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#define ADMA_PORT_REGS(ap) \
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@ -128,7 +128,7 @@ struct adma_port_priv {
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adma_state_t state;
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};
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static int adma_ata_init_one (struct pci_dev *pdev,
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static int adma_ata_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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static int adma_port_start(struct ata_port *ap);
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static void adma_host_stop(struct ata_host *host);
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@ -340,8 +340,8 @@ static int adma_fill_sg(struct ata_queued_cmd *qc)
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buf[i++] = 0; /* pPKLW */
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buf[i++] = 0; /* reserved */
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*(__le32 *)(buf + i)
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= (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
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*(__le32 *)(buf + i) =
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(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
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i += 4;
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VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
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@ -617,7 +617,7 @@ static int adma_port_start(struct ata_port *ap)
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return -ENOMEM;
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/* paranoia? */
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if ((pp->pkt_dma & 7) != 0) {
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printk("bad alignment for pp->pkt_dma: %08x\n",
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printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
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(u32)pp->pkt_dma);
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return -ENOMEM;
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}
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@ -143,7 +143,7 @@ static const int scr_map[] = {
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[SCR_CONTROL] = 2,
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};
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static void __iomem * inic_port_base(struct ata_port *ap)
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static void __iomem *inic_port_base(struct ata_port *ap)
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{
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return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
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}
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@ -1156,7 +1156,7 @@ static void mv_fill_sg(struct ata_queued_cmd *qc)
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last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
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}
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static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
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static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
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{
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u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
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(last ? CRQB_CMD_LAST : 0);
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@ -2429,7 +2429,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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struct mv_host_priv *hpriv = host->private_data;
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u32 hp_flags = hpriv->hp_flags;
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switch(board_idx) {
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switch (board_idx) {
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case chip_5080:
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hpriv->ops = &mv5xxx_ops;
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hp_flags |= MV_HP_GEN_I;
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@ -2510,7 +2510,8 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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break;
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default:
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printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
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dev_printk(KERN_ERR, &pdev->dev,
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"BUG: invalid board index %u\n", board_idx);
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return 1;
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}
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@ -291,7 +291,7 @@ struct nv_swncq_port_priv {
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};
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#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
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#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
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static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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#ifdef CONFIG_PM
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@ -884,8 +884,9 @@ static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
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/* Notifier bits set without a command may indicate the drive
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is misbehaving. Raise host state machine violation on this
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condition. */
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ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n",
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cpb_num);
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ata_port_printk(ap, KERN_ERR,
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"notifier for tag %d with no cmd?\n",
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cpb_num);
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ehi->err_mask |= AC_ERR_HSM;
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ehi->action |= ATA_EH_SOFTRESET;
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ata_port_freeze(ap);
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@ -1021,8 +1022,8 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
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while ((pos = ffs(check_commands)) && !error) {
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pos--;
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error = nv_adma_check_cpb(ap, pos,
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notifier_error & (1 << pos) );
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check_commands &= ~(1 << pos );
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notifier_error & (1 << pos));
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check_commands &= ~(1 << pos);
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}
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}
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}
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@ -1061,7 +1062,7 @@ static void nv_adma_freeze(struct ata_port *ap)
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tmp = readw(mmio + NV_ADMA_CTL);
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writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
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mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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}
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static void nv_adma_thaw(struct ata_port *ap)
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@ -1079,7 +1080,7 @@ static void nv_adma_thaw(struct ata_port *ap)
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tmp = readw(mmio + NV_ADMA_CTL);
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writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
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mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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}
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static void nv_adma_irq_clear(struct ata_port *ap)
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@ -1165,7 +1166,7 @@ static int nv_adma_port_start(struct ata_port *ap)
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pp->cpb_dma = mem_dma;
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writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
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writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
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writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
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mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
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mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
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@ -1189,15 +1190,15 @@ static int nv_adma_port_start(struct ata_port *ap)
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/* clear GO for register mode, enable interrupt */
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tmp = readw(mmio + NV_ADMA_CTL);
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writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
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NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
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NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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tmp = readw(mmio + NV_ADMA_CTL);
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writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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udelay(1);
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writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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return 0;
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}
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@ -1237,7 +1238,7 @@ static int nv_adma_port_resume(struct ata_port *ap)
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/* set CPB block location */
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writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
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writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
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writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
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/* clear any outstanding interrupt conditions */
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writew(0xffff, mmio + NV_ADMA_STAT);
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@ -1250,15 +1251,15 @@ static int nv_adma_port_resume(struct ata_port *ap)
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/* clear GO for register mode, enable interrupt */
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tmp = readw(mmio + NV_ADMA_CTL);
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writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
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NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
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NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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tmp = readw(mmio + NV_ADMA_CTL);
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writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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udelay(1);
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writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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readw(mmio + NV_ADMA_CTL ); /* flush posted write */
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readw(mmio + NV_ADMA_CTL); /* flush posted write */
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return 0;
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}
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@ -1342,7 +1343,8 @@ static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
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idx = 0;
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ata_for_each_sg(sg, qc) {
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aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
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aprd = (idx < 5) ? &cpb->aprd[idx] :
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&pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
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nv_adma_fill_aprd(qc, sg, idx, aprd);
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idx++;
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}
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@ -1407,8 +1409,8 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
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} else
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memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
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/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
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finished filling in all of the contents */
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/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
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until we are finished filling in all of the contents */
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wmb();
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cpb->ctl_flags = ctl_flags;
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wmb();
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@ -1436,15 +1438,15 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
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wmb();
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if (curr_ncq != pp->last_issue_ncq) {
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/* Seems to need some delay before switching between NCQ and non-NCQ
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commands, else we get command timeouts and such. */
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/* Seems to need some delay before switching between NCQ and
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non-NCQ commands, else we get command timeouts and such. */
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udelay(20);
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pp->last_issue_ncq = curr_ncq;
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}
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writew(qc->tag, mmio + NV_ADMA_APPEND);
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DPRINTK("Issued tag %u\n",qc->tag);
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DPRINTK("Issued tag %u\n", qc->tag);
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return 0;
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}
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@ -1654,7 +1656,8 @@ static void nv_adma_error_handler(struct ata_port *ap)
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u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
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u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
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ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
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ata_port_printk(ap, KERN_ERR,
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"EH in ADMA mode, notifier 0x%X "
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"notifier_error 0x%X gen_ctl 0x%X status 0x%X "
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"next cpb count 0x%X next cpb idx 0x%x\n",
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notifier, notifier_error, gen_ctl, status,
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@ -1663,7 +1666,7 @@ static void nv_adma_error_handler(struct ata_port *ap)
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for (i = 0; i < NV_ADMA_MAX_CPBS; i++) {
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struct nv_adma_cpb *cpb = &pp->cpb[i];
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if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
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ap->link.sactive & (1 << i) )
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ap->link.sactive & (1 << i))
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ata_port_printk(ap, KERN_ERR,
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"CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
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i, cpb->ctl_flags, cpb->resp_flags);
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@ -1673,7 +1676,8 @@ static void nv_adma_error_handler(struct ata_port *ap)
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/* Push us back into port register mode for error handling. */
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nv_adma_register_mode(ap);
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/* Mark all of the CPBs as invalid to prevent them from being executed */
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/* Mark all of the CPBs as invalid to prevent them from
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being executed */
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for (i = 0; i < NV_ADMA_MAX_CPBS; i++)
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pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
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@ -2350,9 +2354,9 @@ static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
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return IRQ_RETVAL(handled);
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}
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version = 0;
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static int printed_version;
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const struct ata_port_info *ppi[] = { NULL, NULL };
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struct ata_host *host;
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struct nv_host_priv *hpriv;
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@ -2364,7 +2368,7 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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// Make sure this is a SATA controller by counting the number of bars
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// (NVIDIA SATA controllers will always have six bars). Otherwise,
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// it's an IDE controller and we ignore it.
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for (bar=0; bar<6; bar++)
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for (bar = 0; bar < 6; bar++)
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if (pci_resource_start(pdev, bar) == 0)
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return -ENODEV;
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@ -2460,17 +2464,17 @@ static int nv_pci_device_resume(struct pci_dev *pdev)
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pp = host->ports[0]->private_data;
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if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
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tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
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NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
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NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
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else
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tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
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NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
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NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
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pp = host->ports[1]->private_data;
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if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
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tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
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NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
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NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
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else
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tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
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NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
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NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
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|
||||
pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -83,10 +83,12 @@ enum {
|
|||
PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
|
||||
PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
|
||||
PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
|
||||
PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
|
||||
PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
|
||||
| PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
|
||||
| PDC1_ERR_MASK | PDC2_ERR_MASK),
|
||||
PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
|
||||
PDC2_ATA_DMA_CNT_ERR,
|
||||
PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
|
||||
PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
|
||||
PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
|
||||
PDC1_ERR_MASK | PDC2_ERR_MASK,
|
||||
|
||||
board_2037x = 0, /* FastTrak S150 TX2plus */
|
||||
board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
|
||||
|
|
@ -695,19 +697,20 @@ static void pdc_irq_clear(struct ata_port *ap)
|
|||
readl(mmio + PDC_INT_SEQMASK);
|
||||
}
|
||||
|
||||
static inline int pdc_is_sataii_tx4(unsigned long flags)
|
||||
static int pdc_is_sataii_tx4(unsigned long flags)
|
||||
{
|
||||
const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
|
||||
return (flags & mask) == mask;
|
||||
}
|
||||
|
||||
static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4)
|
||||
static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
|
||||
int is_sataii_tx4)
|
||||
{
|
||||
static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
|
||||
return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
|
||||
}
|
||||
|
||||
static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
|
||||
static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
|
||||
{
|
||||
struct ata_host *host = dev_instance;
|
||||
struct ata_port *ap;
|
||||
|
|
@ -839,15 +842,16 @@ static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
|
|||
|
||||
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_ATAPI_DMA);
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_ATAPI_DMA);
|
||||
ata_tf_load(ap, tf);
|
||||
}
|
||||
|
||||
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
static void pdc_exec_command_mmio(struct ata_port *ap,
|
||||
const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_ATAPI_DMA);
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_ATAPI_DMA);
|
||||
ata_exec_command(ap, tf);
|
||||
}
|
||||
|
||||
|
|
@ -870,8 +874,11 @@ static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
|
|||
}
|
||||
/* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
|
||||
if (scsicmd[0] == WRITE_10) {
|
||||
unsigned int lba;
|
||||
lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
|
||||
unsigned int lba =
|
||||
(scsicmd[2] << 24) |
|
||||
(scsicmd[3] << 16) |
|
||||
(scsicmd[4] << 8) |
|
||||
scsicmd[5];
|
||||
if (lba >= 0xFFFF4FA2)
|
||||
pio = 1;
|
||||
}
|
||||
|
|
@ -956,7 +963,8 @@ static void pdc_host_init(struct ata_host *host)
|
|||
writel(tmp, mmio + PDC_SLEW_CTL);
|
||||
}
|
||||
|
||||
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int pdc_ata_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ struct qs_port_priv {
|
|||
|
||||
static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int qs_port_start(struct ata_port *ap);
|
||||
static void qs_host_stop(struct ata_host *host);
|
||||
static void qs_phy_reset(struct ata_port *ap);
|
||||
|
|
@ -135,7 +135,6 @@ static struct scsi_host_template qs_ata_sht = {
|
|||
.sg_tablesize = QS_MAX_PRD,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
//FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.proc_name = DRV_NAME,
|
||||
.dma_boundary = QS_DMA_BOUNDARY,
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ enum {
|
|||
SIL_QUIRK_UDMA5MAX = (1 << 1),
|
||||
};
|
||||
|
||||
static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
#ifdef CONFIG_PM
|
||||
static int sil_pci_device_resume(struct pci_dev *pdev);
|
||||
#endif
|
||||
|
|
@ -138,7 +138,7 @@ static const struct pci_device_id sil_pci_tbl[] = {
|
|||
|
||||
/* TODO firmware versions should be added - eric */
|
||||
static const struct sil_drivelist {
|
||||
const char * product;
|
||||
const char *product;
|
||||
unsigned int quirk;
|
||||
} sil_blacklist [] = {
|
||||
{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
|
||||
|
|
@ -279,7 +279,7 @@ MODULE_LICENSE("GPL");
|
|||
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
||||
static int slow_down = 0;
|
||||
static int slow_down;
|
||||
module_param(slow_down, int, 0444);
|
||||
MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
|
||||
|
||||
|
|
@ -332,7 +332,8 @@ static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
|
||||
static inline void __iomem *sil_scr_addr(struct ata_port *ap,
|
||||
unsigned int sc_reg)
|
||||
{
|
||||
void __iomem *offset = ap->ioaddr.scr_addr;
|
||||
|
||||
|
|
@ -643,7 +644,7 @@ static void sil_init_controller(struct ata_host *host)
|
|||
}
|
||||
}
|
||||
|
||||
static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
int board_id = ent->driver_data;
|
||||
|
|
|
|||
|
|
@ -674,7 +674,7 @@ static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
/* put the port into known state */
|
||||
if (sil24_init_port(ap)) {
|
||||
reason ="port not ready";
|
||||
reason = "port not ready";
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
@ -756,7 +756,8 @@ static int sil24_hardreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
|
||||
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
||||
PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
|
||||
PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
|
||||
tout_msec);
|
||||
|
||||
/* SStatus oscillates between zero and valid status after
|
||||
* DEV_RST, debounce it.
|
||||
|
|
@ -1270,7 +1271,7 @@ static void sil24_init_controller(struct ata_host *host)
|
|||
PORT_CS_PORT_RST, 10, 100);
|
||||
if (tmp & PORT_CS_PORT_RST)
|
||||
dev_printk(KERN_ERR, host->dev,
|
||||
"failed to clear port RST\n");
|
||||
"failed to clear port RST\n");
|
||||
}
|
||||
|
||||
/* configure port */
|
||||
|
|
@ -1283,7 +1284,7 @@ static void sil24_init_controller(struct ata_host *host)
|
|||
|
||||
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version = 0;
|
||||
static int printed_version;
|
||||
struct ata_port_info pi = sil24_port_info[ent->driver_data];
|
||||
const struct ata_port_info *ppi[] = { &pi, NULL };
|
||||
void __iomem * const *iomap;
|
||||
|
|
|
|||
|
|
@ -63,17 +63,17 @@ enum {
|
|||
GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
|
||||
};
|
||||
|
||||
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int sis_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
|
||||
static const struct pci_device_id sis_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
|
||||
{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
|
||||
{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
|
||||
{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
|
||||
{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
|
||||
{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
|
||||
{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
|
||||
{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
|
||||
{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
|
||||
{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
|
||||
{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
|
||||
{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
|
||||
|
||||
{ } /* terminate list */
|
||||
};
|
||||
|
|
@ -149,24 +149,24 @@ static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
|
|||
|
||||
if (ap->port_no) {
|
||||
switch (pdev->device) {
|
||||
case 0x0180:
|
||||
case 0x0181:
|
||||
pci_read_config_byte(pdev, SIS_PMR, &pmr);
|
||||
if ((pmr & SIS_PMR_COMBINED) == 0)
|
||||
addr += SIS180_SATA1_OFS;
|
||||
break;
|
||||
case 0x0180:
|
||||
case 0x0181:
|
||||
pci_read_config_byte(pdev, SIS_PMR, &pmr);
|
||||
if ((pmr & SIS_PMR_COMBINED) == 0)
|
||||
addr += SIS180_SATA1_OFS;
|
||||
break;
|
||||
|
||||
case 0x0182:
|
||||
case 0x0183:
|
||||
case 0x1182:
|
||||
addr += SIS182_SATA1_OFS;
|
||||
break;
|
||||
case 0x0182:
|
||||
case 0x0183:
|
||||
case 0x1182:
|
||||
addr += SIS182_SATA1_OFS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
|
|
@ -190,7 +190,7 @@ static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
|
|
@ -253,7 +253,7 @@ static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
struct ata_port_info pi = sis_port_info;
|
||||
|
|
@ -309,29 +309,33 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
} else {
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"Detected SiS 180/181 chipset in combined mode\n");
|
||||
port2_start=0;
|
||||
port2_start = 0;
|
||||
pi.flags |= ATA_FLAG_SLAVE_POSS;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x0182:
|
||||
case 0x0183:
|
||||
pci_read_config_dword ( pdev, 0x6C, &val);
|
||||
pci_read_config_dword(pdev, 0x6C, &val);
|
||||
if (val & (1L << 31)) {
|
||||
dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"Detected SiS 182/965 chipset\n");
|
||||
pi.flags |= ATA_FLAG_SLAVE_POSS;
|
||||
} else {
|
||||
dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"Detected SiS 182/965L chipset\n");
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x1182:
|
||||
dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/966/680 SATA controller\n");
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"Detected SiS 1182/966/680 SATA controller\n");
|
||||
pi.flags |= ATA_FLAG_SLAVE_POSS;
|
||||
break;
|
||||
|
||||
case 0x1183:
|
||||
dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
|
||||
ppi[0] = &sis_info133_for_sata;
|
||||
ppi[1] = &sis_info133_for_sata;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|||
tf->hob_lbal = lbal >> 8;
|
||||
tf->hob_lbam = lbam >> 8;
|
||||
tf->hob_lbah = lbah >> 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -193,7 +193,7 @@ static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|||
* spin_lock_irqsave(host lock)
|
||||
*/
|
||||
|
||||
static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
|
||||
static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
||||
|
|
@ -224,7 +224,7 @@ static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
|
|||
* spin_lock_irqsave(host lock)
|
||||
*/
|
||||
|
||||
static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
|
||||
static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
||||
|
|
@ -255,7 +255,7 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
|
|||
|
||||
static u8 k2_stat_check_status(struct ata_port *ap)
|
||||
{
|
||||
return readl(ap->ioaddr.status_addr);
|
||||
return readl(ap->ioaddr.status_addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_OF
|
||||
|
|
@ -395,7 +395,7 @@ static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
|
|||
}
|
||||
|
||||
|
||||
static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
const struct ata_port_info *ppi[] =
|
||||
|
|
|
|||
|
|
@ -212,9 +212,9 @@ struct pdc_host_priv {
|
|||
};
|
||||
|
||||
|
||||
static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static void pdc_eng_timeout(struct ata_port *ap);
|
||||
static void pdc_20621_phy_reset (struct ata_port *ap);
|
||||
static void pdc_20621_phy_reset(struct ata_port *ap);
|
||||
static int pdc_port_start(struct ata_port *ap);
|
||||
static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
|
||||
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
|
||||
|
|
@ -320,16 +320,16 @@ static int pdc_port_start(struct ata_port *ap)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void pdc_20621_phy_reset (struct ata_port *ap)
|
||||
static void pdc_20621_phy_reset(struct ata_port *ap)
|
||||
{
|
||||
VPRINTK("ENTER\n");
|
||||
ap->cbl = ATA_CBL_SATA;
|
||||
ata_port_probe(ap);
|
||||
ata_bus_reset(ap);
|
||||
ap->cbl = ATA_CBL_SATA;
|
||||
ata_port_probe(ap);
|
||||
ata_bus_reset(ap);
|
||||
}
|
||||
|
||||
static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
|
||||
unsigned int portno,
|
||||
unsigned int portno,
|
||||
unsigned int total_len)
|
||||
{
|
||||
u32 addr;
|
||||
|
|
@ -351,7 +351,7 @@ static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
|
|||
}
|
||||
|
||||
static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
|
||||
unsigned int portno,
|
||||
unsigned int portno,
|
||||
unsigned int total_len)
|
||||
{
|
||||
u32 addr;
|
||||
|
|
@ -711,8 +711,8 @@ static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
|
|||
return ata_qc_issue_prot(qc);
|
||||
}
|
||||
|
||||
static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
|
||||
struct ata_queued_cmd *qc,
|
||||
static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
|
||||
struct ata_queued_cmd *qc,
|
||||
unsigned int doing_hdma,
|
||||
void __iomem *mmio)
|
||||
{
|
||||
|
|
@ -803,7 +803,7 @@ static void pdc20621_irq_clear(struct ata_port *ap)
|
|||
readl(mmio + PDC_20621_SEQMASK);
|
||||
}
|
||||
|
||||
static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
|
||||
static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
|
||||
{
|
||||
struct ata_host *host = dev_instance;
|
||||
struct ata_port *ap;
|
||||
|
|
@ -836,9 +836,9 @@ static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
|
|||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
spin_lock(&host->lock);
|
||||
spin_lock(&host->lock);
|
||||
|
||||
for (i = 1; i < 9; i++) {
|
||||
for (i = 1; i < 9; i++) {
|
||||
port_no = i - 1;
|
||||
if (port_no > 3)
|
||||
port_no -= 4;
|
||||
|
|
@ -859,7 +859,7 @@ static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
|
|||
}
|
||||
}
|
||||
|
||||
spin_unlock(&host->lock);
|
||||
spin_unlock(&host->lock);
|
||||
|
||||
VPRINTK("mask == 0x%x\n", mask);
|
||||
|
||||
|
|
@ -906,16 +906,16 @@ static void pdc_eng_timeout(struct ata_port *ap)
|
|||
|
||||
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
ata_tf_load(ap, tf);
|
||||
}
|
||||
|
||||
|
||||
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
ata_exec_command(ap, tf);
|
||||
}
|
||||
|
||||
|
|
@ -953,7 +953,7 @@ static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
|
|||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
page_mask = 0x00;
|
||||
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
||||
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
||||
idx = (u16) (offset / window_size);
|
||||
|
||||
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
||||
|
|
@ -979,7 +979,7 @@ static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
|
|||
window_size / 4);
|
||||
psource += window_size;
|
||||
size -= window_size;
|
||||
idx ++;
|
||||
idx++;
|
||||
}
|
||||
|
||||
if (size) {
|
||||
|
|
@ -1008,7 +1008,7 @@ static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
|
|||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
page_mask = 0x00;
|
||||
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
||||
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
||||
idx = (u16) (offset / window_size);
|
||||
|
||||
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
||||
|
|
@ -1031,7 +1031,7 @@ static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
|
|||
readl(mmio + PDC_GENERAL_CTLR);
|
||||
psource += window_size;
|
||||
size -= window_size;
|
||||
idx ++;
|
||||
idx++;
|
||||
}
|
||||
|
||||
if (size) {
|
||||
|
|
@ -1050,7 +1050,7 @@ static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
|
|||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
u32 i2creg = 0;
|
||||
u32 status;
|
||||
u32 count =0;
|
||||
u32 count = 0;
|
||||
|
||||
/* hard-code chip #0 */
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
|
|
@ -1082,21 +1082,21 @@ static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
|
|||
|
||||
static int pdc20621_detect_dimm(struct ata_host *host)
|
||||
{
|
||||
u32 data=0 ;
|
||||
u32 data = 0;
|
||||
if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
|
||||
PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
|
||||
if (data == 100)
|
||||
if (data == 100)
|
||||
return 100;
|
||||
} else
|
||||
} else
|
||||
return 0;
|
||||
|
||||
if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
|
||||
if (data <= 0x75)
|
||||
return 133;
|
||||
} else
|
||||
} else
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1104,8 +1104,8 @@ static int pdc20621_prog_dimm0(struct ata_host *host)
|
|||
{
|
||||
u32 spd0[50];
|
||||
u32 data = 0;
|
||||
int size, i;
|
||||
u8 bdimmsize;
|
||||
int size, i;
|
||||
u8 bdimmsize;
|
||||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
static const struct {
|
||||
unsigned int reg;
|
||||
|
|
@ -1128,40 +1128,40 @@ static int pdc20621_prog_dimm0(struct ata_host *host)
|
|||
/* hard-code chip #0 */
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
|
||||
for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
|
||||
pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
|
||||
pdc_i2c_read_data[i].reg,
|
||||
&spd0[pdc_i2c_read_data[i].ofs]);
|
||||
|
||||
data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
|
||||
data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
|
||||
data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
|
||||
data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
|
||||
((((spd0[27] + 9) / 10) - 1) << 8) ;
|
||||
data |= (((((spd0[29] > spd0[28])
|
||||
data |= (((((spd0[29] > spd0[28])
|
||||
? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
|
||||
data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
|
||||
data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
|
||||
|
||||
if (spd0[18] & 0x08)
|
||||
if (spd0[18] & 0x08)
|
||||
data |= ((0x03) << 14);
|
||||
else if (spd0[18] & 0x04)
|
||||
else if (spd0[18] & 0x04)
|
||||
data |= ((0x02) << 14);
|
||||
else if (spd0[18] & 0x01)
|
||||
else if (spd0[18] & 0x01)
|
||||
data |= ((0x01) << 14);
|
||||
else
|
||||
else
|
||||
data |= (0 << 14);
|
||||
|
||||
/*
|
||||
/*
|
||||
Calculate the size of bDIMMSize (power of 2) and
|
||||
merge the DIMM size by program start/end address.
|
||||
*/
|
||||
|
||||
bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
|
||||
size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
|
||||
data |= (((size / 16) - 1) << 16);
|
||||
data |= (0 << 23);
|
||||
bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
|
||||
size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
|
||||
data |= (((size / 16) - 1) << 16);
|
||||
data |= (0 << 23);
|
||||
data |= 8;
|
||||
writel(data, mmio + PDC_DIMM0_CONTROL);
|
||||
writel(data, mmio + PDC_DIMM0_CONTROL);
|
||||
readl(mmio + PDC_DIMM0_CONTROL);
|
||||
return size;
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1172,9 +1172,9 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
|
|||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
|
||||
/* hard-code chip #0 */
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
/*
|
||||
/*
|
||||
Set To Default : DIMM Module Global Control Register (0x022259F1)
|
||||
DIMM Arbitration Disable (bit 20)
|
||||
DIMM Data/Control Output Driving Selection (bit12 - bit15)
|
||||
|
|
@ -1193,40 +1193,40 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
|
|||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
readl(mmio + PDC_SDRAM_CONTROL);
|
||||
printk(KERN_ERR "Local DIMM ECC Enabled\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* DIMM Initialization Select/Enable (bit 18/19) */
|
||||
data &= (~(1<<18));
|
||||
data |= (1<<19);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
/* DIMM Initialization Select/Enable (bit 18/19) */
|
||||
data &= (~(1<<18));
|
||||
data |= (1<<19);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
|
||||
error = 1;
|
||||
for (i = 1; i <= 10; i++) { /* polling ~5 secs */
|
||||
error = 1;
|
||||
for (i = 1; i <= 10; i++) { /* polling ~5 secs */
|
||||
data = readl(mmio + PDC_SDRAM_CONTROL);
|
||||
if (!(data & (1<<19))) {
|
||||
error = 0;
|
||||
break;
|
||||
error = 0;
|
||||
break;
|
||||
}
|
||||
msleep(i*100);
|
||||
}
|
||||
return error;
|
||||
}
|
||||
return error;
|
||||
}
|
||||
|
||||
|
||||
static unsigned int pdc20621_dimm_init(struct ata_host *host)
|
||||
{
|
||||
int speed, size, length;
|
||||
u32 addr,spd0,pci_status;
|
||||
u32 tmp=0;
|
||||
u32 time_period=0;
|
||||
u32 tcount=0;
|
||||
u32 ticks=0;
|
||||
u32 clock=0;
|
||||
u32 fparam=0;
|
||||
u32 addr, spd0, pci_status;
|
||||
u32 tmp = 0;
|
||||
u32 time_period = 0;
|
||||
u32 tcount = 0;
|
||||
u32 ticks = 0;
|
||||
u32 clock = 0;
|
||||
u32 fparam = 0;
|
||||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
|
||||
/* hard-code chip #0 */
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
/* Initialize PLL based upon PCI Bus Frequency */
|
||||
|
||||
|
|
@ -1285,41 +1285,43 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
|
|||
if (!(speed = pdc20621_detect_dimm(host))) {
|
||||
printk(KERN_ERR "Detect Local DIMM Fail\n");
|
||||
return 1; /* DIMM error */
|
||||
}
|
||||
VPRINTK("Local DIMM Speed = %d\n", speed);
|
||||
}
|
||||
VPRINTK("Local DIMM Speed = %d\n", speed);
|
||||
|
||||
/* Programming DIMM0 Module Control Register (index_CID0:80h) */
|
||||
/* Programming DIMM0 Module Control Register (index_CID0:80h) */
|
||||
size = pdc20621_prog_dimm0(host);
|
||||
VPRINTK("Local DIMM Size = %dMB\n",size);
|
||||
VPRINTK("Local DIMM Size = %dMB\n", size);
|
||||
|
||||
/* Programming DIMM Module Global Control Register (index_CID0:88h) */
|
||||
/* Programming DIMM Module Global Control Register (index_CID0:88h) */
|
||||
if (pdc20621_prog_dimm_global(host)) {
|
||||
printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef ATA_VERBOSE_DEBUG
|
||||
{
|
||||
u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
|
||||
'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
|
||||
'1','.','1','0',
|
||||
'9','8','0','3','1','6','1','2',0,0};
|
||||
u8 test_parttern1[40] =
|
||||
{0x55,0xAA,'P','r','o','m','i','s','e',' ',
|
||||
'N','o','t',' ','Y','e','t',' ',
|
||||
'D','e','f','i','n','e','d',' ',
|
||||
'1','.','1','0',
|
||||
'9','8','0','3','1','6','1','2',0,0};
|
||||
u8 test_parttern2[40] = {0};
|
||||
|
||||
pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
|
||||
pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
|
||||
pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
|
||||
pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
|
||||
|
||||
pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
|
||||
pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
|
||||
pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
|
||||
pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
|
||||
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
||||
test_parttern2[1], &(test_parttern2[2]));
|
||||
pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
|
||||
pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
|
||||
40);
|
||||
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
||||
test_parttern2[1], &(test_parttern2[2]));
|
||||
|
||||
pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
|
||||
pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
|
||||
pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
|
||||
pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
|
||||
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
||||
test_parttern2[1], &(test_parttern2[2]));
|
||||
}
|
||||
|
|
@ -1375,7 +1377,8 @@ static void pdc_20621_init(struct ata_host *host)
|
|||
readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
|
||||
}
|
||||
|
||||
static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int pdc_sata_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
const struct ata_port_info *ppi[] =
|
||||
|
|
|
|||
|
|
@ -56,9 +56,9 @@ struct uli_priv {
|
|||
unsigned int scr_cfg_addr[uli_max_ports];
|
||||
};
|
||||
|
||||
static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int uli_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int uli_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int uli_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
|
||||
static const struct pci_device_id uli_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(AL, 0x5289), uli_5289 },
|
||||
|
|
@ -143,7 +143,7 @@ static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
|
|||
return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
|
||||
}
|
||||
|
||||
static u32 uli_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
|
||||
static u32 uli_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
|
|
@ -153,7 +153,7 @@ static u32 uli_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
|
|||
return val;
|
||||
}
|
||||
|
||||
static void uli_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
|
||||
static void uli_scr_cfg_write(struct ata_port *ap, unsigned int scr, u32 val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, scr);
|
||||
|
|
@ -161,7 +161,7 @@ static void uli_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
|
|||
pci_write_config_dword(pdev, cfg_addr, val);
|
||||
}
|
||||
|
||||
static int uli_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int uli_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
|
|
@ -170,16 +170,16 @@ static int uli_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int uli_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
|
||||
if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
|
||||
return -EINVAL;
|
||||
|
||||
uli_scr_cfg_write(ap, sc_reg, val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Maintained by: Jeff Garzik <jgarzik@pobox.com>
|
||||
* Please ALWAYS copy linux-ide@vger.kernel.org
|
||||
on emails.
|
||||
* on emails.
|
||||
*
|
||||
* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
|
||||
* Copyright 2003-2004 Jeff Garzik
|
||||
|
|
@ -69,7 +69,7 @@ enum {
|
|||
SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
|
||||
};
|
||||
|
||||
static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static void svia_noop_freeze(struct ata_port *ap);
|
||||
|
|
@ -372,12 +372,12 @@ static const unsigned int vt6421_bar_sizes[] = {
|
|||
16, 16, 16, 16, 32, 128
|
||||
};
|
||||
|
||||
static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port)
|
||||
static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
|
||||
{
|
||||
return addr + (port * 128);
|
||||
}
|
||||
|
||||
static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port)
|
||||
static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
|
||||
{
|
||||
return addr + (port * 64);
|
||||
}
|
||||
|
|
@ -472,7 +472,7 @@ static void svia_configure(struct pci_dev *pdev)
|
|||
if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
|
||||
dev_printk(KERN_DEBUG, &pdev->dev,
|
||||
"enabling SATA channels (0x%x)\n",
|
||||
(int) tmp8);
|
||||
(int) tmp8);
|
||||
tmp8 |= ALL_PORTS;
|
||||
pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
|
||||
}
|
||||
|
|
@ -482,7 +482,7 @@ static void svia_configure(struct pci_dev *pdev)
|
|||
if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
|
||||
dev_printk(KERN_DEBUG, &pdev->dev,
|
||||
"enabling SATA channel interrupts (0x%x)\n",
|
||||
(int) tmp8);
|
||||
(int) tmp8);
|
||||
tmp8 |= ALL_PORTS;
|
||||
pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
|
||||
}
|
||||
|
|
@ -492,13 +492,13 @@ static void svia_configure(struct pci_dev *pdev)
|
|||
if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
|
||||
dev_printk(KERN_DEBUG, &pdev->dev,
|
||||
"enabling SATA channel native mode (0x%x)\n",
|
||||
(int) tmp8);
|
||||
(int) tmp8);
|
||||
tmp8 |= NATIVE_MODE_ALL;
|
||||
pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
|
||||
}
|
||||
}
|
||||
|
||||
static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
unsigned int i;
|
||||
|
|
@ -525,8 +525,8 @@ static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
|
||||
i,
|
||||
(unsigned long long)pci_resource_start(pdev, i),
|
||||
(unsigned long long)pci_resource_len(pdev, i));
|
||||
(unsigned long long)pci_resource_start(pdev, i),
|
||||
(unsigned long long)pci_resource_len(pdev, i));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,8 @@ static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
|
|||
/*
|
||||
* The only thing the ctl register is used for is SRST.
|
||||
* That is not enabled or disabled via tf_load.
|
||||
* However, if ATA_NIEN is changed, then we need to change the interrupt register.
|
||||
* However, if ATA_NIEN is changed, then we need to change
|
||||
* the interrupt register.
|
||||
*/
|
||||
if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
|
||||
ap->last_ctl = tf->ctl;
|
||||
|
|
@ -219,7 +220,7 @@ static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|||
tf->hob_lbal = lbal >> 8;
|
||||
tf->hob_lbam = lbam >> 8;
|
||||
tf->hob_lbah = lbah >> 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
|
||||
|
|
@ -256,9 +257,10 @@ static void vsc_port_intr(u8 port_status, struct ata_port *ap)
|
|||
/*
|
||||
* vsc_sata_interrupt
|
||||
*
|
||||
* Read the interrupt register and process for the devices that have them pending.
|
||||
* Read the interrupt register and process for the devices that have
|
||||
* them pending.
|
||||
*/
|
||||
static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
|
||||
static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
|
||||
{
|
||||
struct ata_host *host = dev_instance;
|
||||
unsigned int i;
|
||||
|
|
@ -287,7 +289,7 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
|
|||
handled++;
|
||||
} else
|
||||
dev_printk(KERN_ERR, host->dev,
|
||||
": interrupt from disabled port %d\n", i);
|
||||
"interrupt from disabled port %d\n", i);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -363,7 +365,8 @@ static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
|
|||
}
|
||||
|
||||
|
||||
static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
static int __devinit vsc_sata_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
static const struct ata_port_info pi = {
|
||||
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
|
||||
|
|
|
|||
Reference in New Issue