[Blackfin] arch: remove useless IRQ_SW_INT defines
IRQ_SW_INT1 and IRQ_SW_INT2 obsolete: Remove useless defines Fix SYS_IRQS Keep numbering scheme, so we don't break existing configurations. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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3 changed files with 28 additions and 34 deletions
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@ -66,12 +66,13 @@ Core Emulation **
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DMA8/9 Interrupt IVG13 28
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DMA10/11 Interrupt IVG13 29
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Watchdog Timer IVG13 30
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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Softirq IVG14 31
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System Call --
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(lowest priority) IVG15 32 *
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*/
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#define SYS_IRQS 32
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#define NR_PERI_INTS 24
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#define SYS_IRQS 31
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#define NR_PERI_INTS 24
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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@ -96,7 +97,7 @@ Core Emulation **
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#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
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#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
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#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
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#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
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#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
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#define IRQ_TMR0 23 /*Timer 0 */
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@ -108,9 +109,6 @@ Core Emulation **
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#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
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#define IRQ_WATCH 30 /*Watch Dog Timer */
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#define IRQ_SW_INT1 31 /*Software Int 1 */
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#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
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#define IRQ_PF0 33
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#define IRQ_PF1 34
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#define IRQ_PF2 35
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@ -34,24 +34,23 @@
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/*
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* Interrupt source definitions
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Event Source Core Event Name
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Core Emulation **
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Events (highest priority) EMU 0
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Reset RST 1
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NMI NMI 2
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Exception EVX 3
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Reserved -- 4
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Hardware Error IVHW 5
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Core Timer IVTMR 6 *
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.....
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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(lowest priority) IVG15 32 *
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* Event Source Core Event Name
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* Core Emulation **
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* Events (highest priority) EMU 0
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* Reset RST 1
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* NMI NMI 2
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* Exception EVX 3
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* Reserved -- 4
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* Hardware Error IVHW 5
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* Core Timer IVTMR 6
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* .....
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*
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* Softirq IVG14
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* System Call --
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* (lowest priority) IVG15
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*/
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#define SYS_IRQS 41
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#define SYS_IRQS 39
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#define NR_PERI_INTS 32
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/* The ABSTRACT IRQ definitions */
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@ -95,10 +94,8 @@ Core Emulation **
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#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
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#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
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#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
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#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
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#define IRQ_WATCH 38 /*Watch Dog Timer */
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#define IRQ_SW_INT1 40 /*Software Int 1 */
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#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
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#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
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@ -118,12 +118,13 @@
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Supplemental interrupt 0 IVG7 69
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supplemental interrupt 1 IVG7 70
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Software Interrupt 1 IVG14 71
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Software Interrupt 2 IVG15 72 *
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(lowest priority)
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Softirq IVG14
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System Call --
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(lowest priority) IVG15
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**********************************************************************/
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#define SYS_IRQS 72
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#define SYS_IRQS 71
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#define NR_PERI_INTS 64
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/*
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@ -237,9 +238,7 @@
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#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
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#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
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#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
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#define IRQ_SW_INT1 71 /* Software Interrupt 1 */
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#define IRQ_SW_INT2 72 /* Software Interrupt 2 */
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/* reserved for SYSCALL */
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#define IRQ_PF0 73
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#define IRQ_PF1 74
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#define IRQ_PF2 75
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