Merge branch 'samsung/devel-2' into late/soc
From Kukjin Kim <kgene.kim@samsung.com>: The updating cpufreq for 1.7GHz of exynos5250 has been included in samsung tree because Rafael thought it was more related in samsung platform and I agreed. And others are adding G2D clock for exynos4x12 Socs. * samsung/devel-2: ARM: S3C64XX: Add header file protection macros in pm-core.h [CPUFREQ] EXYNOS5250: Add support max 1.7GHz for EXYNOS5250 ARM: EXYNOS: Add G2D related clock entries for SMDK4X12 ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file Originally from git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git next/devel-samsung-2 but rebased to split out the defconfig changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
537cd80cea
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@ -619,10 +619,6 @@ static struct clk exynos4_init_clocks_off[] = {
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.devname = "samsung-ac97",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 27),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "mfc",
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.devname = "s5p-mfc",
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@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = {
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[1] = &exynos4_clk_sclk_apll.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
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struct clksrc_sources exynos4_clkset_mout_g2d0 = {
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.sources = exynos4_clkset_mout_g2d0_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
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};
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static struct clksrc_clk exynos4_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clk *exynos4_clkset_mout_g2d1_list[] = {
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[0] = &exynos4_clk_mout_epll.clk,
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[1] = &exynos4_clk_sclk_vpll.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
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struct clksrc_sources exynos4_clkset_mout_g2d1 = {
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.sources = exynos4_clkset_mout_g2d1_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
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};
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static struct clksrc_clk exynos4_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *exynos4_clkset_mout_g2d_list[] = {
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[0] = &exynos4_clk_mout_g2d0.clk,
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[1] = &exynos4_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d = {
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.sources = exynos4_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
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};
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static struct clk *exynos4_clkset_mout_mfc0_list[] = {
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[0] = &exynos4_clk_mout_mpll.clk,
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[1] = &exynos4_clk_sclk_apll.clk,
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@ -1124,13 +1094,6 @@ static struct clksrc_clk exynos4_clksrcs[] = {
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mfc",
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@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group;
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extern struct clk *exynos4_clkset_aclk_top_list[];
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extern struct clk *exynos4_clkset_group_list[];
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extern struct clksrc_sources exynos4_clkset_mout_g2d0;
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extern struct clksrc_sources exynos4_clkset_mout_g2d1;
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extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
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@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = {
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/* nothing here yet */
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *exynos4210_clkset_mout_g2d_list[] = {
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[0] = &exynos4210_clk_mout_g2d0.clk,
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[1] = &exynos4210_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4210_clkset_mout_g2d = {
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.sources = exynos4210_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
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};
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static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
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@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4210_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
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},
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};
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@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = {
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.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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},
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};
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@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = {
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.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
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};
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static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
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};
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static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
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};
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static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
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[0] = &exynos4x12_clk_mout_g2d0.clk,
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[1] = &exynos4x12_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
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.sources = exynos4x12_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
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};
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_mpll_user,
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};
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static struct clksrc_clk clksrcs[] = {
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/* nothing here yet */
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{
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4x12_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
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},
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};
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static struct clk init_clocks_off[] = {
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@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = {
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.devname = "exynos-fimc-lite.1",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 3),
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}
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_dmc_ctrl,
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.ctrlbit = (1 << 23),
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},
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};
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#ifdef CONFIG_PM_SLEEP
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@ -12,6 +12,9 @@
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_S3C64XX_PM_CORE_H
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#define __MACH_S3C64XX_PM_CORE_H __FILE__
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#include <mach/regs-gpio.h>
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static inline void s3c_pm_debug_init_uart(void)
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@ -113,3 +116,4 @@ static inline void samsung_pm_saved_gpios(void)
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__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
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}
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#endif /* __MACH_S3C64XX_PM_CORE_H */
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@ -65,20 +65,20 @@ static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
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* Clock divider value for following
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* { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
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*/
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1700 MHz - N/A */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1600 MHz - N/A */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1500 MHz - N/A */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1400 MHz */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
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{ 0, 2, 7, 7, 5, 1, 2, 0 }, /* 1100 MHz */
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{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
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{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
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{ 0, 2, 7, 7, 3, 1, 1, 0 }, /* 800 MHz */
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{ 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */
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{ 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */
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{ 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
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{ 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
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{ 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
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{ 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 600 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 400 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
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};
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@ -87,9 +87,9 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
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/* Clock divider value for following
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* { COPY, HPM }
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*/
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{ 0, 2 }, /* 1700 MHz - N/A */
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{ 0, 2 }, /* 1600 MHz - N/A */
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{ 0, 2 }, /* 1500 MHz - N/A */
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{ 0, 2 }, /* 1700 MHz */
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{ 0, 2 }, /* 1600 MHz */
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{ 0, 2 }, /* 1500 MHz */
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{ 0, 2 }, /* 1400 MHz */
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{ 0, 2 }, /* 1300 MHz */
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{ 0, 2 }, /* 1200 MHz */
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@ -106,10 +106,10 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
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};
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static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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(0), /* 1700 MHz - N/A */
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(0), /* 1600 MHz - N/A */
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(0), /* 1500 MHz - N/A */
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(0), /* 1400 MHz */
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((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
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((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
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((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
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((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
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((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
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((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
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((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
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@ -126,9 +126,10 @@ static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* ASV group voltage table */
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static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
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0, 0, 0, 0, 0, 0, 0, /* 1700 MHz ~ 1100 MHz Not supported */
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1175000, 1125000, 1075000, 1050000, 1000000,
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950000, 925000, 925000, 900000
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1300000, 1250000, 1225000, 1200000, 1150000,
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1125000, 1100000, 1075000, 1050000, 1025000,
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1012500, 1000000, 975000, 950000, 937500,
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925000
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};
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static void set_clkdiv(unsigned int div_index)
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@ -248,15 +249,7 @@ static void __init set_volt_table(void)
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{
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unsigned int i;
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exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
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max_support_idx = L7;
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max_support_idx = L0;
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for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
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exynos5250_volt_table[i] = asv_voltage_5250[i];
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