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Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4263/1: fix IXP4XX_NPE[ABC]_BASE_VIRT address
  [ARM] 4256/1: i.MX/MX1 SDHC fix/workaround of SD card recognition problems
  [ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
  [ARM] 4254/1: i.MX/MX1 CPU Frequency scaling honor boot loader set BCLK_DIV.
  [ARM] 4251/1: Fix sharpsl_pm dependency
  [ARM] 4250/1: Fix locomo backlight conversion error/compile failure
  [ARM] 4249/1: Fix tosa compile failure
  [ARM] 4248/1: lh7a40x: fix missing definitions for get_irqnr_preamble
  [ARM] 4247/1: Fix long name for cc9p9360dev
  ARM: OMAP: Fix OMAP2 dss2 so clk_set_parent works
  ARM: OMAP: Fix missing workqueue include in board-h2.c
  ARM: OMAP: Include missing header
This commit is contained in:
Linus Torvalds 2007-03-12 12:31:43 -07:00
parent be521466fe 1dee79087c
commit 529284a0b6
12 changed files with 50 additions and 20 deletions
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1
arch/arm/common/Kconfig
View File

@ -28,6 +28,7 @@ config SHARP_PARAM
config SHARPSL_PM
bool
select APM_EMULATION
config SHARP_SCOOP
bool

15
arch/arm/mach-imx/cpufreq.c
View File

@ -50,6 +50,7 @@
#define CR_920T_ASYNC_MODE 0xC0000000
static u32 mpctl0_at_boot;
static u32 bclk_div_at_boot;
static void imx_set_async_mode(void)
{
@ -82,13 +83,13 @@ static void imx_set_mpctl0(u32 mpctl0)
* imx_compute_mpctl - compute new PLL parameters
* @new_mpctl: pointer to location assigned by new PLL control register value
* @cur_mpctl: current PLL control register parameters
* @f_ref: reference source frequency Hz
* @freq: required frequency in Hz
* @relation: is one of %CPUFREQ_RELATION_L (supremum)
* and %CPUFREQ_RELATION_H (infimum)
*/
long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation)
long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation)
{
u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
u32 mfi;
u32 mfn;
u32 mfd;
@ -182,7 +183,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
unsigned long flags;
long freq;
long sysclk;
unsigned int bclk_div = 1;
unsigned int bclk_div = bclk_div_at_boot;
/*
* Some governors do not respects CPU and policy lower limits
@ -202,8 +203,8 @@ static int imx_set_target(struct cpufreq_policy *policy,
sysclk = imx_get_system_clk();
if (freq > sysclk + 1000000) {
freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
if (freq > sysclk / bclk_div_at_boot + 1000000) {
freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
if (freq < 0) {
printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
return -EINVAL;
@ -217,6 +218,8 @@ static int imx_set_target(struct cpufreq_policy *policy,
if(bclk_div > 16)
bclk_div = 16;
if(bclk_div < bclk_div_at_boot)
bclk_div = bclk_div_at_boot;
}
freq = (sysclk + bclk_div / 2) / bclk_div;
}
@ -285,7 +288,7 @@ static struct cpufreq_driver imx_driver = {
static int __init imx_cpufreq_init(void)
{
bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
mpctl0_at_boot = 0;
if((CSCR & CSCR_MPEN) &&

9
arch/arm/mach-imx/generic.c
View File

@ -102,7 +102,7 @@ EXPORT_SYMBOL(imx_gpio_mode);
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll)
static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
{
unsigned long long ll;
unsigned long quot;
@ -111,7 +111,6 @@ static unsigned int imx_decode_pll(unsigned int pll)
u32 mfn = pll & 0x3ff;
u32 mfd = (pll >> 16) & 0x3ff;
u32 pd = (pll >> 26) & 0xf;
u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
mfi = mfi <= 5 ? 5 : mfi;
@ -124,13 +123,15 @@ static unsigned int imx_decode_pll(unsigned int pll)
unsigned int imx_get_system_clk(void)
{
return imx_decode_pll(SPCTL0);
u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
return imx_decode_pll(SPCTL0, f_ref);
}
EXPORT_SYMBOL(imx_get_system_clk);
unsigned int imx_get_mcu_clk(void)
{
return imx_decode_pll(MPCTL0);
return imx_decode_pll(MPCTL0, CLK32 * 512);
}
EXPORT_SYMBOL(imx_get_mcu_clk);

2
arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
View File

@ -32,7 +32,7 @@ static void __init mach_cc9p9360dev_init_machine(void)
board_a9m9750dev_init_machine();
}
MACHINE_START(CC9P9360DEV, "Connect Core 9P 9360 on an A9M9750 Devboard")
MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
.map_io = mach_cc9p9360dev_map_io,
.init_irq = mach_cc9p9360dev_init_irq,
.init_machine = mach_cc9p9360dev_init_machine,

1
arch/arm/mach-omap1/board-h2.c
View File

@ -27,6 +27,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>

1
arch/arm/mach-omap2/clock.c
View File

@ -27,6 +27,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
#include <asm/div64.h>
#include "prcm-regs.h"
#include "memory.h"

3
arch/arm/mach-omap2/clock.h
View File

@ -1013,7 +1013,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.name = "dss2_fck",
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
DELAYED_APP,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 1,
.src_offset = 13,

3
arch/arm/mach-pxa/tosa.c
View File

@ -28,6 +28,7 @@
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
@ -35,8 +36,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/tosa.h>
#include <asm/hardware/scoop.h>

13
drivers/mmc/imxmmc.c
View File

@ -569,10 +569,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
if(host->dma_dir == DMA_FROM_DEVICE) {
imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE,
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
STATUS_TIME_OUT_READ,
50, "imxmci_cpu_driven_data read");
while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
!(stat & STATUS_TIME_OUT_READ) &&
(host->data_cnt < 512)) {
udelay(20); /* required for clocks < 8MHz*/
@ -602,6 +604,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
if(host->dma_size & 0x1ff)
stat &= ~STATUS_CRC_READ_ERR;
if(stat & STATUS_TIME_OUT_READ) {
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
stat);
trans_done = -1;
}
} else {
imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FE,
@ -709,6 +717,9 @@ static void imxmci_tasklet_fnc(unsigned long data)
*/
stat |= host->status_reg;
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
stat &= ~STATUS_CRC_READ_ERR;
if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
imxmci_busy_wait_for_status(host, &stat,
STATUS_END_CMD_RESP | STATUS_ERR_MASK,

4
drivers/video/backlight/locomolcd.c
View File

@ -199,8 +199,8 @@ static int locomolcd_remove(struct locomo_dev *dev)
{
unsigned long flags;
locomobl_data.brightness = 0;
locomobl_data.power = 0;
locomolcd_bl_device->props.brightness = 0;
locomolcd_bl_device->props.power = 0;
locomolcd_set_intensity(locomolcd_bl_device);
backlight_device_unregister(locomolcd_bl_device);

6
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
View File

@ -144,9 +144,9 @@
#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)

12
include/asm-arm/arch-lh7a40x/entry-macro.S
View File

@ -86,6 +86,12 @@ branch_irq_lh7a400: b 1000f
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mov \base, #io_p2v(0x80000000) @ APB registers
@ -105,6 +111,12 @@ branch_irq_lh7a400: b 1000f
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0 @ VIC1 irq base
mov \base, #io_p2v(0x80000000) @ APB registers