Merge branch 'clock_devel_3.7' into hwmod_prcm_clock_a_3.7
Conflicts: arch/arm/mach-omap2/clkt34xx_dpll3m2.c arch/arm/mach-omap2/clkt_clksel.c arch/arm/mach-omap2/clock.c
This commit is contained in:
Paul Walmsley
commit
4fb85d35bc
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@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
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return;
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}
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clk_enable(gpmc_fck);
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clk_prepare_enable(gpmc_fck);
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rate = clk_get_rate(gpmc_fck);
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eth_cs = APOLLON_ETH_CS;
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@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
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gpmc_cs_free(APOLLON_ETH_CS);
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}
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out:
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clk_disable(gpmc_fck);
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clk_disable_unprepare(gpmc_fck);
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clk_put(gpmc_fck);
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}
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@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
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return;
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}
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clk_enable(gpmc_fck);
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clk_prepare_enable(gpmc_fck);
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rate = clk_get_rate(gpmc_fck);
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clk_disable(gpmc_fck);
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clk_disable_unprepare(gpmc_fck);
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clk_put(gpmc_fck);
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if (is_gpmc_muxed())
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@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
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gpmc_cs_free(eth_cs);
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out:
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clk_disable(gpmc_fck);
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clk_disable_unprepare(gpmc_fck);
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clk_put(gpmc_fck);
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}
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@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
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return;
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}
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clk_set_rate(phy_ref_clk, 19200000);
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clk_enable(phy_ref_clk);
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clk_prepare_enable(phy_ref_clk);
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/* disable the power to the usb hub prior to init and reset phy+hub */
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ret = gpio_request_array(panda_ehci_gpios,
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@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
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omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
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OMAP24XX_CM_IDLEST_VAL, clk->name);
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OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
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/*
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* REVISIT: Should we return an error code if omap2_wait_clock_ready()
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@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
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long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
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{
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const struct prcm_config *ptr;
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long highest_rate;
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long highest_rate, sys_clk_rate;
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highest_rate = -EINVAL;
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sys_clk_rate = __clk_get_rate(sclk);
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for (ptr = rate_table; ptr->mpu_speed; ptr++) {
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if (!(ptr->flags & cpu_mask))
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continue;
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if (ptr->xtal_speed != sclk->rate)
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if (ptr->xtal_speed != sys_clk_rate)
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continue;
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highest_rate = ptr->mpu_speed;
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@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
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const struct prcm_config *prcm;
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unsigned long found_speed = 0;
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unsigned long flags;
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long sys_clk_rate;
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sys_clk_rate = __clk_get_rate(sclk);
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for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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if (!(prcm->flags & cpu_mask))
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continue;
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if (prcm->xtal_speed != sclk->rate)
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if (prcm->xtal_speed != sys_clk_rate)
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continue;
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if (prcm->mpu_speed <= rate) {
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@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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struct omap_sdrc_params *sdrc_cs0;
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struct omap_sdrc_params *sdrc_cs1;
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int ret;
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unsigned long clkrate;
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if (!clk || !rate)
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return -EINVAL;
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@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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if (validrate != rate)
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return -EINVAL;
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sdrcrate = sdrc_ick_p->rate;
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if (rate > clk->rate)
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sdrcrate <<= ((rate / clk->rate) >> 1);
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sdrcrate = __clk_get_rate(sdrc_ick_p);
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clkrate = __clk_get_rate(clk);
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if (rate > clkrate)
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sdrcrate <<= ((rate / clkrate) >> 1);
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else
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sdrcrate >>= ((clk->rate / rate) >> 1);
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sdrcrate >>= ((clkrate / rate) >> 1);
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ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
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if (ret)
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@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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/*
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* XXX This only needs to be done when the CPU frequency changes
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*/
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_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
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_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
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c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
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c += 1; /* for safety */
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c *= SDRC_MPURATE_LOOPS;
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@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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if (c == 0)
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c = 1;
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
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clkrate, validrate);
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pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
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@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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if (sdrc_cs1)
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clk->rate,
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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else
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clk->rate,
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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0, 0, 0, 0);
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@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
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if (!clks->parent) {
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/* This indicates a data problem */
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WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
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clk->name, src_clk->name);
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__clk_get_name(clk), __clk_get_name(src_clk));
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return NULL;
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}
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@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
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if (max_div == 0) {
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/* This indicates an error in the clksel data */
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WARN(1, "clock: %s: could not find divisor for parent %s\n",
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clk->name, src_clk->parent->name);
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__clk_get_name(clk),
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__clk_get_name(__clk_get_parent(src_clk)));
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return 0;
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}
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@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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struct clk *parent;
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clks = _get_clksel_by_parent(clk, clk->parent);
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parent = __clk_get_parent(clk);
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return 0;
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@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
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if (!clkr->div) {
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/* This indicates a data error */
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WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
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clk->name, field_val, clk->parent->name);
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WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
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__clk_get_name(clk), field_val, __clk_get_name(parent));
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return 0;
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}
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@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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struct clk *parent;
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/* should never happen */
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WARN_ON(div == 0);
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clks = _get_clksel_by_parent(clk, clk->parent);
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parent = __clk_get_parent(clk);
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return ~0;
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@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
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}
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if (!clkr->div) {
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pr_err("clock: %s: could not find divisor %d parent %s\n",
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clk->name, div, clk->parent->name);
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pr_err("clock: %s: could not find divisor %d for parent %s\n",
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__clk_get_name(clk), div, __clk_get_name(parent));
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return ~0;
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}
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@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 last_div = 0;
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struct clk *parent;
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unsigned long parent_rate;
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const char *clk_name;
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parent = __clk_get_parent(clk);
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parent_rate = __clk_get_rate(parent);
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clk_name = __clk_get_name(clk);
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if (!clk->clksel || !clk->clksel_mask)
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return ~0;
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pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk->name, target_rate);
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clk_name, target_rate);
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*new_div = 1;
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clks = _get_clksel_by_parent(clk, clk->parent);
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return ~0;
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@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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/* Sanity check */
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if (clkr->div <= last_div)
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pr_err("clock: %s: clksel_rate table not sorted",
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clk->name);
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pr_err("clock: %s: clksel_rate table not sorted\n",
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clk_name);
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last_div = clkr->div;
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test_rate = clk->parent->rate / clkr->div;
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test_rate = parent_rate / clkr->div;
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if (test_rate <= target_rate)
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break; /* found it */
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}
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if (!clkr->div) {
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pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
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clk->name, target_rate, clk->parent->name);
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pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
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clk_name, target_rate, __clk_get_name(parent));
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return ~0;
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}
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*new_div = clkr->div;
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pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
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(clk->parent->rate / clkr->div));
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(parent_rate / clkr->div));
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return clk->parent->rate / clkr->div;
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return parent_rate / clkr->div;
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}
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/*
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@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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struct clk *parent;
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const char *clk_name;
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if (!clk->clksel || !clk->clksel_mask)
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return;
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parent = __clk_get_parent(clk);
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clk_name = __clk_get_name(clk);
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk)
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continue;
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if (clkr->val == r) {
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if (clk->parent != clks->parent) {
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if (parent != clks->parent) {
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pr_debug("clock: %s: inited parent to %s (was %s)\n",
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clk->name, clks->parent->name,
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((clk->parent) ?
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clk->parent->name : "NULL"));
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clk_name,
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__clk_get_name(clks->parent),
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((parent) ?
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__clk_get_name(parent) :
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"NULL"));
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clk_reparent(clk, clks->parent);
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};
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found = 1;
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@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
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/* This indicates a data error */
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WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
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clk->name, r);
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clk_name, r);
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return;
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}
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@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
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u32 div = 0;
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struct clk *parent;
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div = _read_divisor(clk);
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if (div == 0)
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return clk->rate;
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return __clk_get_rate(clk);
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rate = clk->parent->rate / div;
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parent = __clk_get_parent(clk);
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rate = __clk_get_rate(parent) / div;
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pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
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rate, div);
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pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
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__clk_get_name(clk), rate, div);
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return rate;
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}
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@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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_write_clksel_reg(clk, field_val);
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clk->rate = clk->parent->rate / new_div;
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clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
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pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
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pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
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__clk_get_rate(clk));
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return 0;
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}
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@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
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clk_reparent(clk, new_parent);
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/* CLKSEL clocks follow their parents' rates, divided by a divisor */
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clk->rate = new_parent->rate;
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clk->rate = __clk_get_rate(new_parent);
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if (parent_div > 0)
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clk->rate /= parent_div;
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__clk_get_rate(clk) /= parent_div;
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pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
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clk->name, clk->parent->name, clk->rate);
|
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__clk_get_name(clk),
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__clk_get_name(__clk_get_parent(clk)),
|
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__clk_get_rate(clk));
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|
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return 0;
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}
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|
|
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|
|
@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
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dd = clk->dpll_data;
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|
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/* DPLL divider must result in a valid jitter correction val */
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fint = clk->parent->rate / n;
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fint = __clk_get_rate(__clk_get_parent(clk)) / n;
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if (cpu_is_omap24xx()) {
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/* Should not be called for OMAP2, so warn if it is called */
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||||
|
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@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
|
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
|
||||
return dd->clk_bypass->rate;
|
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return __clk_get_rate(dd->clk_bypass);
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} else if (cpu_is_omap34xx()) {
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
return dd->clk_bypass->rate;
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return __clk_get_rate(dd->clk_bypass);
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||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
return dd->clk_bypass->rate;
|
||||
return __clk_get_rate(dd->clk_bypass);
|
||||
}
|
||||
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
|
|
@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
|
|||
dpll_div = v & dd->div1_mask;
|
||||
dpll_div >>= __ffs(dd->div1_mask);
|
||||
|
||||
dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
|
||||
dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
|
||||
do_div(dpll_clk, dpll_div + 1);
|
||||
|
||||
return dpll_clk;
|
||||
|
|
@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
|||
unsigned long scaled_rt_rp;
|
||||
unsigned long new_rate = 0;
|
||||
struct dpll_data *dd;
|
||||
unsigned long ref_rate;
|
||||
const char *clk_name;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return ~0;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
ref_rate = __clk_get_rate(dd->clk_ref);
|
||||
clk_name = __clk_get_name(clk);
|
||||
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
|
||||
clk->name, target_rate);
|
||||
clk_name, target_rate);
|
||||
|
||||
scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
|
||||
scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
|
||||
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
|
||||
|
||||
dd->last_rounded_rate = 0;
|
||||
|
|
@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
|||
break;
|
||||
|
||||
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
|
||||
dd->clk_ref->rate);
|
||||
ref_rate);
|
||||
|
||||
/* m can't be set low enough for this n - try with a larger n */
|
||||
if (r == DPLL_MULT_UNDERFLOW)
|
||||
continue;
|
||||
|
||||
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
|
||||
clk->name, m, n, new_rate);
|
||||
clk_name, m, n, new_rate);
|
||||
|
||||
if (target_rate == new_rate) {
|
||||
dd->last_rounded_m = m;
|
||||
|
|
@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
|||
}
|
||||
|
||||
if (target_rate != new_rate) {
|
||||
pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
|
||||
target_rate);
|
||||
pr_debug("clock: %s: cannot round to rate %ld\n",
|
||||
clk_name, target_rate);
|
||||
return ~0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
|
|||
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
|
||||
|
||||
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
|
||||
clk->name);
|
||||
__clk_get_name(clk));
|
||||
}
|
||||
|
||||
/* Public functions */
|
||||
|
|
@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
|
|||
void omap2_init_clk_clkdm(struct clk *clk)
|
||||
{
|
||||
struct clockdomain *clkdm;
|
||||
const char *clk_name;
|
||||
|
||||
if (!clk->clkdm_name)
|
||||
return;
|
||||
|
||||
clk_name = __clk_get_name(clk);
|
||||
|
||||
clkdm = clkdm_lookup(clk->clkdm_name);
|
||||
if (clkdm) {
|
||||
pr_debug("clock: associated clk %s to clkdm %s\n",
|
||||
clk->name, clk->clkdm_name);
|
||||
clk_name, clk->clkdm_name);
|
||||
clk->clkdm = clkdm;
|
||||
} else {
|
||||
pr_debug("clock: could not associate clk %s to clkdm %s\n",
|
||||
clk->name, clk->clkdm_name);
|
||||
clk_name, clk->clkdm_name);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
|
|||
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
|
||||
/* DSS domain clocks */
|
||||
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
|
||||
CLK(NULL, "dss_ick", &dss_ick, CK_242X),
|
||||
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
|
||||
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
|
||||
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
|
||||
|
|
@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
|
|||
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
|
||||
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
|
||||
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
|
||||
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
|
||||
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
|
||||
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
|
||||
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
|
||||
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
|
||||
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
|
||||
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
|
||||
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
|
||||
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
|
||||
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
|
||||
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
|
||||
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
|
||||
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
|
||||
|
|
@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
|
|||
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
|
||||
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
|
||||
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
|
||||
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
|
||||
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
|
||||
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
|
||||
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
|
||||
CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
|
||||
CLK(NULL, "cam_fck", &cam_fck, CK_242X),
|
||||
CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
|
||||
CLK(NULL, "cam_ick", &cam_ick, CK_242X),
|
||||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
|
||||
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
|
||||
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
|
||||
|
|
@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
|
|||
CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
|
||||
CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
|
||||
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
|
||||
CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
|
||||
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
|
||||
CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
|
||||
CLK(NULL, "fac_ick", &fac_ick, CK_242X),
|
||||
CLK(NULL, "fac_fck", &fac_fck, CK_242X),
|
||||
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
|
||||
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
|
||||
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
|
||||
CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
|
||||
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
|
||||
CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
|
||||
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
|
||||
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
|
||||
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
|
||||
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
|
||||
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
|
||||
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
|
||||
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
|
||||
|
|
@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
|
|||
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
|
||||
CLK(NULL, "des_ick", &des_ick, CK_242X),
|
||||
CLK("omap-sham", "ick", &sha_ick, CK_242X),
|
||||
CLK(NULL, "sha_ick", &sha_ick, CK_242X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_242X),
|
||||
CLK(NULL, "rng_ick", &rng_ick, CK_242X),
|
||||
CLK("omap-aes", "ick", &aes_ick, CK_242X),
|
||||
CLK(NULL, "aes_ick", &aes_ick, CK_242X),
|
||||
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
|
||||
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
|
||||
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
|
||||
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
|
||||
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
|
||||
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
|
||||
CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
|
||||
CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
|
||||
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
|
|||
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
|
||||
/* DSS domain clocks */
|
||||
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
|
||||
CLK(NULL, "dss_ick", &dss_ick, CK_243X),
|
||||
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
|
||||
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
|
||||
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
|
||||
|
|
@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
|
|||
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
|
||||
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
|
||||
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
|
||||
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
|
||||
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
|
||||
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
|
||||
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
|
||||
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
|
||||
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
|
||||
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
|
||||
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
|
||||
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
|
||||
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
|
||||
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
|
||||
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
|
||||
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
|
||||
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
|
||||
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
|
||||
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
|
||||
|
|
@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
|
|||
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
|
||||
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
|
||||
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
|
||||
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
|
||||
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
|
||||
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
|
||||
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
|
||||
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
|
||||
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
|
||||
CLK(NULL, "cam_fck", &cam_fck, CK_243X),
|
||||
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
|
||||
CLK(NULL, "cam_ick", &cam_ick, CK_243X),
|
||||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
|
||||
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
|
||||
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
|
||||
|
|
@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
|
|||
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
|
||||
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
|
||||
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
|
||||
CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
|
||||
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
|
||||
CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
|
||||
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
|
||||
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
|
||||
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
|
||||
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
|
||||
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
|
||||
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
|
||||
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
|
||||
|
|
@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
|
|||
CLK(NULL, "des_ick", &des_ick, CK_243X),
|
||||
CLK("omap-sham", "ick", &sha_ick, CK_243X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_243X),
|
||||
CLK(NULL, "rng_ick", &rng_ick, CK_243X),
|
||||
CLK("omap-aes", "ick", &aes_ick, CK_243X),
|
||||
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
|
||||
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
|
||||
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
|
||||
CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
|
||||
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
|
||||
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
|
||||
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
|
||||
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
|
||||
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
|
||||
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
|
||||
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
|
||||
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
|
||||
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
||||
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
||||
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
|
||||
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
|
||||
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
|
||||
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
|
|||
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
|
||||
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
|
||||
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
|
||||
CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
|
||||
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
|
||||
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
|
||||
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
|
||||
|
|
|
|||
|
|
@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
|
|||
|
||||
dpll5_clk = clk_get(NULL, "dpll5_ck");
|
||||
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
|
||||
clk_enable(dpll5_clk);
|
||||
clk_prepare_enable(dpll5_clk);
|
||||
|
||||
/* Program dpll5_m2_clk divider for no division */
|
||||
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
|
||||
clk_enable(dpll5_m2_clk);
|
||||
clk_prepare_enable(dpll5_m2_clk);
|
||||
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
|
||||
|
||||
clk_disable(dpll5_m2_clk);
|
||||
clk_disable(dpll5_clk);
|
||||
clk_disable_unprepare(dpll5_m2_clk);
|
||||
clk_disable_unprepare(dpll5_clk);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
|
|||
* clkdev
|
||||
*/
|
||||
|
||||
/* XXX At some point we should rename this file to clock3xxx_data.c */
|
||||
static struct omap_clk omap3xxx_clks[] = {
|
||||
CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
|
||||
CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
|
||||
|
|
@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
|
||||
CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
|
||||
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
|
||||
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
|
||||
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
|
||||
CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
|
||||
CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
|
||||
CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
|
||||
CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
|
||||
|
|
@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
|
||||
CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
|
||||
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
|
|
@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
|
||||
CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
|
||||
CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
|
||||
CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
|
||||
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
|
||||
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
|
||||
|
|
@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
|
||||
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
|
||||
|
|
@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
|
||||
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
|
||||
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
|
||||
CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
|
||||
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
|
||||
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
|
||||
|
|
@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
|
||||
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
|
||||
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
|
||||
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
|
||||
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
|
||||
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
|
||||
|
|
@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
|
||||
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
|
||||
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
|
||||
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
|
||||
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
|
||||
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
|
||||
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
|
||||
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
|
||||
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
|
||||
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
|
||||
CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
|
||||
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
|
||||
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
|
||||
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
|
||||
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
|
||||
CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
|
||||
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
|
||||
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
|
||||
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
|
||||
CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
|
||||
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
|
||||
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
|
||||
CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
|
||||
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
|
||||
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
|
||||
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
|
||||
CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
|
||||
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
|
||||
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
|
||||
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
|
||||
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
|
||||
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
|
||||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
|
||||
|
|
@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
|
||||
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
|
||||
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
|
||||
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
||||
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
|
||||
|
|
@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
|
||||
CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
|
||||
CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
|
||||
CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
|
||||
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
|
||||
CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
|
||||
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
|
||||
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
|
||||
|
|
@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
|
||||
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
|
||||
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
|
||||
CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
|
||||
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
|
||||
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
|
||||
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
|
||||
|
|
@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
|
||||
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
|
||||
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
|
||||
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
|
||||
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
|
||||
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
|
||||
CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
|
||||
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
|
||||
CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
|
||||
CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
|
||||
|
|
@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
|
||||
CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
|
||||
CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
|
||||
CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
|
||||
CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
|
||||
CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
|
||||
CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
|
||||
CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX),
|
||||
CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX),
|
||||
CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
|
||||
CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
|
||||
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
|
||||
|
|
@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
|
|||
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
|
||||
CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
|
||||
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
|
||||
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
|
||||
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
|
||||
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
|
||||
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
|
||||
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
|
||||
|
|
@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
|
||||
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
|
||||
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
|
||||
CLK(NULL, "rng_ick", &rng_ick, CK_443X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_443X),
|
||||
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
|
||||
CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
|
||||
|
|
@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
|
||||
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
|
||||
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
|
||||
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
|
||||
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
|
||||
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
|
||||
|
|
@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
|
||||
CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
|
||||
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
|
||||
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
|
||||
CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
|
||||
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
|
||||
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
|
||||
CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
||||
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
||||
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
|
||||
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
|
||||
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
|
||||
|
|
@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
|
||||
/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
|
||||
CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
|
|
@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
|
||||
};
|
||||
|
||||
int __init omap4xxx_clk_init(void)
|
||||
|
|
|
|||
|
|
@ -25,263 +25,328 @@
|
|||
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
|
||||
#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
|
||||
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
|
||||
#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
|
||||
#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_CPSW_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_CEFUSE_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_GFX_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_GFX_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
|
||||
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
|
||||
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
|
||||
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
|
||||
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
|
||||
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
|
||||
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
|
||||
#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_PRUSS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
|
||||
|
||||
/* Used by CM_PER_L3S_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_L3_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_L4FW_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_PER_L4HS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CEFUSE_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_RTC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
|
||||
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
|
||||
#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
|
||||
|
||||
/* Used by CM_PER_LCDC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_LCDC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
|
||||
#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
|
||||
|
||||
/* Used by CM_PER_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_MPU_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
|
||||
#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
|
||||
|
||||
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_RTC_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
|
||||
#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
|
||||
#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
|
||||
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
|
||||
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
|
||||
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
|
||||
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
|
||||
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
|
||||
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
|
||||
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
|
||||
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
|
||||
#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_PER_L4LS_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
|
||||
#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
|
||||
#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_WKUP_CLKSTCTRL */
|
||||
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
|
||||
#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
|
||||
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
|
||||
#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2DIV_SHIFT 3
|
||||
#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
|
||||
#define AM33XX_CLKOUT2DIV_WIDTH 3
|
||||
#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2EN_SHIFT 7
|
||||
#define AM33XX_CLKOUT2EN_WIDTH 1
|
||||
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
|
||||
|
||||
/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
|
||||
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
|
||||
|
|
@ -289,6 +354,7 @@
|
|||
* CLKSEL_TIMER7_CLK
|
||||
*/
|
||||
#define AM33XX_CLKSEL_SHIFT 0
|
||||
#define AM33XX_CLKSEL_WIDTH 1
|
||||
#define AM33XX_CLKSEL_MASK (0x01 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -296,17 +362,21 @@
|
|||
* CM_CPTS_RFT_CLKSEL
|
||||
*/
|
||||
#define AM33XX_CLKSEL_0_0_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_0_WIDTH 1
|
||||
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
|
||||
|
||||
#define AM33XX_CLKSEL_0_1_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_1_WIDTH 2
|
||||
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
|
||||
|
||||
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
|
||||
#define AM33XX_CLKSEL_0_2_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_2_WIDTH 3
|
||||
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
|
||||
|
||||
/*
|
||||
|
|
@ -318,6 +388,7 @@
|
|||
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
|
||||
*/
|
||||
#define AM33XX_CLKTRCTRL_SHIFT 0
|
||||
#define AM33XX_CLKTRCTRL_WIDTH 2
|
||||
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -326,34 +397,42 @@
|
|||
* CM_SSC_DELTAMSTEP_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DELTAMSTEP_SHIFT 0
|
||||
#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
|
||||
#define AM33XX_DELTAMSTEP_WIDTH 20
|
||||
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
|
||||
|
||||
/*
|
||||
|
|
@ -361,6 +440,7 @@
|
|||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -368,19 +448,22 @@
|
|||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_WIDTH 7
|
||||
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
|
||||
|
||||
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
|
||||
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -388,6 +471,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_EN_SHIFT 0
|
||||
#define AM33XX_DPLL_EN_WIDTH 3
|
||||
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -395,6 +479,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
|
||||
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
|
||||
|
||||
/*
|
||||
|
|
@ -402,10 +487,12 @@
|
|||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_MULT_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_WIDTH 11
|
||||
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
|
||||
|
||||
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
|
||||
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -413,17 +500,20 @@
|
|||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
|
||||
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
|
||||
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_SD_DIV_SHIFT 24
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
|
||||
#define AM33XX_DPLL_SD_DIV_WIDTH 8
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
|
||||
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
|
||||
|
||||
/*
|
||||
|
|
@ -431,6 +521,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
|
||||
|
||||
/*
|
||||
|
|
@ -438,54 +529,67 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_SSC_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
|
||||
|
||||
/*
|
||||
|
|
@ -522,11 +626,12 @@
|
|||
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_IDLEST_SHIFT 16
|
||||
#define AM33XX_IDLEST_WIDTH 2
|
||||
#define AM33XX_IDLEST_MASK (0x3 << 16)
|
||||
#define AM33XX_IDLEST_VAL 0x3
|
||||
|
||||
/* Used by CM_MAC_CLKSEL */
|
||||
#define AM33XX_MII_CLK_SEL_SHIFT 2
|
||||
#define AM33XX_MII_CLK_SEL_WIDTH 1
|
||||
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
|
|
@ -535,7 +640,8 @@
|
|||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
|
|
@ -543,7 +649,8 @@
|
|||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
|
|
@ -580,42 +687,52 @@
|
|||
* CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_MODULEMODE_SHIFT 0
|
||||
#define AM33XX_MODULEMODE_WIDTH 2
|
||||
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_WKUP_GPIO0_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO1_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO2_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO3_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO4_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO5_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO6_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/*
|
||||
|
|
@ -627,25 +744,30 @@
|
|||
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_STBYST_SHIFT 18
|
||||
#define AM33XX_STBYST_WIDTH 1
|
||||
#define AM33XX_STBYST_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
|
||||
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLK_SHIFT 0
|
||||
#define AM33XX_ST_DPLL_CLK_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -653,18 +775,22 @@
|
|||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
|
||||
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
|
||||
|
||||
/*
|
||||
|
|
@ -672,16 +798,20 @@
|
|||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_MN_BYPASS_SHIFT 8
|
||||
#define AM33XX_ST_MN_BYPASS_WIDTH 1
|
||||
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
|
||||
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
|
||||
|
||||
/* Used by CONTROL_SEC_CLK_CTRL */
|
||||
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -354,6 +354,7 @@
|
|||
|
||||
/* AM33XX CONTROL_STATUS bitfields (partial) */
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
|
||||
|
||||
/* CONTROL OMAP STATUS register to identify OMAP3 features */
|
||||
|
|
|
|||
|
|
@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
|
|||
|
||||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk)
|
||||
clk_enable(oc->_clk);
|
||||
clk_prepare_enable(oc->_clk);
|
||||
|
||||
dispc_disable_outputs();
|
||||
|
||||
|
|
@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
|
|||
|
||||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk)
|
||||
clk_disable(oc->_clk);
|
||||
clk_disable_unprepare(oc->_clk);
|
||||
|
||||
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
|
|||
const struct dpll_data *dd;
|
||||
int i = 0;
|
||||
int ret = -EINVAL;
|
||||
const char *clk_name;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
clk_name = __clk_get_name(clk);
|
||||
|
||||
state <<= __ffs(dd->idlest_mask);
|
||||
|
||||
|
|
@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
|
|||
|
||||
if (i == MAX_DPLL_WAIT_TRIES) {
|
||||
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
|
||||
clk->name, (state) ? "locked" : "bypassed");
|
||||
clk_name, (state) ? "locked" : "bypassed");
|
||||
} else {
|
||||
pr_debug("clock: %s transition to '%s' in %d loops\n",
|
||||
clk->name, (state) ? "locked" : "bypassed", i);
|
||||
clk_name, (state) ? "locked" : "bypassed", i);
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
|
|
@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
|
|||
unsigned long fint;
|
||||
u16 f = 0;
|
||||
|
||||
fint = clk->dpll_data->clk_ref->rate / n;
|
||||
fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
|
||||
|
||||
pr_debug("clock: fint is %lu\n", fint);
|
||||
|
||||
|
|
@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
|
|||
u8 state = 1;
|
||||
int r = 0;
|
||||
|
||||
pr_debug("clock: locking DPLL %s\n", clk->name);
|
||||
pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
|
||||
|
||||
dd = clk->dpll_data;
|
||||
state <<= __ffs(dd->idlest_mask);
|
||||
|
|
@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
|
|||
return -EINVAL;
|
||||
|
||||
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
|
||||
clk->name);
|
||||
__clk_get_name(clk));
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
||||
|
|
@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
|
|||
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("clock: stopping DPLL %s\n", clk->name);
|
||||
pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
||||
|
|
@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
|
|||
{
|
||||
unsigned long fint, clkinp; /* watch out for overflow */
|
||||
|
||||
clkinp = clk->parent->rate;
|
||||
clkinp = __clk_get_rate(__clk_get_parent(clk));
|
||||
fint = (clkinp / n) * m;
|
||||
|
||||
if (fint < 1000000000)
|
||||
|
|
@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
|
|||
unsigned long clkinp, sd; /* watch out for overflow */
|
||||
int mod1, mod2;
|
||||
|
||||
clkinp = clk->parent->rate;
|
||||
clkinp = __clk_get_rate(__clk_get_parent(clk));
|
||||
|
||||
/*
|
||||
* target sigma-delta to near 250MHz
|
||||
|
|
@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
|
|||
{
|
||||
int r;
|
||||
struct dpll_data *dd;
|
||||
struct clk *parent;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->rate == dd->clk_bypass->rate) {
|
||||
WARN_ON(clk->parent != dd->clk_bypass);
|
||||
parent = __clk_get_parent(clk);
|
||||
|
||||
if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
|
||||
WARN_ON(parent != dd->clk_bypass);
|
||||
r = _omap3_noncore_dpll_bypass(clk);
|
||||
} else {
|
||||
WARN_ON(clk->parent != dd->clk_ref);
|
||||
WARN_ON(parent != dd->clk_ref);
|
||||
r = _omap3_noncore_dpll_lock(clk);
|
||||
}
|
||||
/*
|
||||
|
|
@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
|
|||
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *new_parent = NULL;
|
||||
unsigned long hw_rate;
|
||||
unsigned long hw_rate, bypass_rate;
|
||||
u16 freqsel = 0;
|
||||
struct dpll_data *dd;
|
||||
int ret;
|
||||
|
|
@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
|||
omap2_clk_enable(dd->clk_bypass);
|
||||
omap2_clk_enable(dd->clk_ref);
|
||||
|
||||
if (dd->clk_bypass->rate == rate &&
|
||||
bypass_rate = __clk_get_rate(dd->clk_bypass);
|
||||
if (bypass_rate == rate &&
|
||||
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
|
||||
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
|
||||
|
||||
|
|
@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
|||
}
|
||||
|
||||
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
|
||||
clk->name, rate);
|
||||
__clk_get_name(clk), rate);
|
||||
|
||||
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
|
||||
dd->last_rounded_n, freqsel);
|
||||
|
|
@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
|
|||
|
||||
if (!dd->autoidle_reg) {
|
||||
pr_debug("clock: DPLL %s: autoidle not supported\n",
|
||||
clk->name);
|
||||
__clk_get_name(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
|
|||
|
||||
if (!dd->autoidle_reg) {
|
||||
pr_debug("clock: DPLL %s: autoidle not supported\n",
|
||||
clk->name);
|
||||
__clk_get_name(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
|
|||
unsigned long rate;
|
||||
u32 v;
|
||||
struct clk *pclk;
|
||||
unsigned long parent_rate;
|
||||
|
||||
/* Walk up the parents of clk, looking for a DPLL */
|
||||
pclk = clk->parent;
|
||||
pclk = __clk_get_parent(clk);
|
||||
while (pclk && !pclk->dpll_data)
|
||||
pclk = pclk->parent;
|
||||
pclk = __clk_get_parent(pclk);
|
||||
|
||||
/* clk does not have a DPLL as a parent? error in the clock data */
|
||||
if (!pclk) {
|
||||
|
|
@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
|
|||
|
||||
WARN_ON(!dd->enable_mask);
|
||||
|
||||
parent_rate = __clk_get_rate(__clk_get_parent(clk));
|
||||
v = __raw_readl(dd->control_reg) & dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
|
||||
rate = clk->parent->rate;
|
||||
rate = parent_rate;
|
||||
else
|
||||
rate = clk->parent->rate * 2;
|
||||
rate = parent_rate * 2;
|
||||
return rate;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -879,7 +879,7 @@ static int __init gpmc_init(void)
|
|||
BUG();
|
||||
}
|
||||
|
||||
clk_enable(gpmc_l3_clk);
|
||||
clk_prepare_enable(gpmc_l3_clk);
|
||||
|
||||
l = gpmc_read_reg(GPMC_REVISION);
|
||||
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
|
||||
|
|
|
|||
|
|
@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
|
|||
if (!oh->main_clk)
|
||||
return 0;
|
||||
|
||||
oh->_clk = omap_clk_get_by_name(oh->main_clk);
|
||||
if (!oh->_clk) {
|
||||
oh->_clk = clk_get(NULL, oh->main_clk);
|
||||
if (IS_ERR(oh->_clk)) {
|
||||
pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
|
||||
oh->name, oh->main_clk);
|
||||
return -EINVAL;
|
||||
}
|
||||
/*
|
||||
* HACK: This needs a re-visit once clk_prepare() is implemented
|
||||
* to do something meaningful. Today its just a no-op.
|
||||
* If clk_prepare() is used at some point to do things like
|
||||
* voltage scaling etc, then this would have to be moved to
|
||||
* some point where subsystems like i2c and pmic become
|
||||
* available.
|
||||
*/
|
||||
clk_prepare(oh->_clk);
|
||||
|
||||
if (!oh->_clk->clkdm)
|
||||
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
|
||||
oh->main_clk, oh->_clk->name);
|
||||
oh->name, oh->main_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
|
|||
if (!os->clk)
|
||||
continue;
|
||||
|
||||
c = omap_clk_get_by_name(os->clk);
|
||||
if (!c) {
|
||||
c = clk_get(NULL, os->clk);
|
||||
if (IS_ERR(c)) {
|
||||
pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
|
||||
oh->name, os->clk);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
os->_clk = c;
|
||||
/*
|
||||
* HACK: This needs a re-visit once clk_prepare() is implemented
|
||||
* to do something meaningful. Today its just a no-op.
|
||||
* If clk_prepare() is used at some point to do things like
|
||||
* voltage scaling etc, then this would have to be moved to
|
||||
* some point where subsystems like i2c and pmic become
|
||||
* available.
|
||||
*/
|
||||
clk_prepare(os->_clk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
|
|||
int ret = 0;
|
||||
|
||||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
|
||||
c = omap_clk_get_by_name(oc->clk);
|
||||
if (!c) {
|
||||
c = clk_get(NULL, oc->clk);
|
||||
if (IS_ERR(c)) {
|
||||
pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
|
||||
oh->name, oc->clk);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
oc->_clk = c;
|
||||
/*
|
||||
* HACK: This needs a re-visit once clk_prepare() is implemented
|
||||
* to do something meaningful. Today its just a no-op.
|
||||
* If clk_prepare() is used at some point to do things like
|
||||
* voltage scaling etc, then this would have to be moved to
|
||||
* some point where subsystems like i2c and pmic become
|
||||
* available.
|
||||
*/
|
||||
clk_prepare(oc->_clk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
|
|||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk) {
|
||||
pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
|
||||
oc->_clk->name);
|
||||
__clk_get_name(oc->_clk));
|
||||
clk_enable(oc->_clk);
|
||||
}
|
||||
}
|
||||
|
|
@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
|
|||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk) {
|
||||
pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
|
||||
oc->_clk->name);
|
||||
__clk_get_name(oc->_clk));
|
||||
clk_disable(oc->_clk);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
|||
goto exit;
|
||||
}
|
||||
|
||||
freq = clk->rate;
|
||||
freq = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
rcu_read_lock();
|
||||
|
|
|
|||
|
|
@ -312,33 +312,6 @@ void clk_enable_init_clocks(void)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_clk_get_by_name - locate OMAP struct clk by its name
|
||||
* @name: name of the struct clk to locate
|
||||
*
|
||||
* Locate an OMAP struct clk by its name. Assumes that struct clk
|
||||
* names are unique. Returns NULL if not found or a pointer to the
|
||||
* struct clk if found.
|
||||
*/
|
||||
struct clk *omap_clk_get_by_name(const char *name)
|
||||
{
|
||||
struct clk *c;
|
||||
struct clk *ret = NULL;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
|
||||
list_for_each_entry(c, &clocks, node) {
|
||||
if (!strcmp(c->name, name)) {
|
||||
ret = c;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omap_clk_enable_autoidle_all(void)
|
||||
{
|
||||
struct clk *c;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,11 @@ struct module;
|
|||
struct clk;
|
||||
struct clockdomain;
|
||||
|
||||
/* Temporary, needed during the common clock framework conversion */
|
||||
#define __clk_get_name(clk) (clk->name)
|
||||
#define __clk_get_parent(clk) (clk->parent)
|
||||
#define __clk_get_rate(clk) (clk->rate)
|
||||
|
||||
/**
|
||||
* struct clkops - some clock function pointers
|
||||
* @enable: fn ptr that enables the current clock in hardware
|
||||
|
|
|
|||
|
|
@ -261,10 +261,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
|
|||
return;
|
||||
}
|
||||
|
||||
r = omap_clk_get_by_name(clk_name);
|
||||
r = clk_get(NULL, clk_name);
|
||||
if (IS_ERR(r)) {
|
||||
dev_err(&od->pdev->dev,
|
||||
"omap_clk_get_by_name for %s failed\n", clk_name);
|
||||
"clk_get for %s failed\n", clk_name);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -37,8 +37,6 @@
|
|||
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <plat/clock.h>
|
||||
|
||||
#define OMAP1_SPI100K_MAX_FREQ 48000000
|
||||
|
||||
#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@
|
|||
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/mcspi.h>
|
||||
|
||||
#define OMAP2_MCSPI_MAX_FREQ 48000000
|
||||
|
|
|
|||
Reference in New Issue