Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (21 commits) amd64_edac: bump driver version amd64_edac: fix use-uninitialised bug amd64_edac: correct sys address to chip select mapping amd64_edac: add a leaner syndrome decoding algorithm amd64_edac: remove early hw support check amd64_edac: detect DDR3 memory type edac: add memory types strings for debugging edac, mce: update AMD F10h revD check amd64_edac: remove unneeded extract_error_address wrapper amd64_edac: rename StinkyIdentifier amd64_edac: remove superfluous dbg printk amd64_edac: enhance address to DRAM bank mapping amd64_edac: cleanup f10_early_channel_count amd64_edac: dump DIMM sizes on K8 too amd64_edac: cleanup rest of amd64_dump_misc_regs amd64_edac: cleanup DRAM cfg low debug output amd64_edac: wrap-up pci config read error handling amd64_edac: unify MCGCTL ECC switching cpumask: use modern cpumask style in drivers/edac/amd64_edac.c amd64_edac: make DRAM regions output more human-readable ...
This commit is contained in:
Linus Torvalds
commit
4e5df8069b
File diff suppressed because it is too large
Load Diff
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@ -129,24 +129,22 @@
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* sections 3.5.4 and 3.5.5 for more information.
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*/
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#define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__
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#define EDAC_AMD64_VERSION " Ver: 3.3.0 " __DATE__
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#define EDAC_MOD_STR "amd64_edac"
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#define EDAC_MAX_NUMNODES 8
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/* Extended Model from CPUID, for CPU Revision numbers */
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#define OPTERON_CPU_LE_REV_C 0
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#define OPTERON_CPU_REV_D 1
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#define OPTERON_CPU_REV_E 2
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/* NPT processors have the following Extended Models */
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#define OPTERON_CPU_REV_F 4
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#define OPTERON_CPU_REV_FA 5
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#define K8_REV_D 1
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#define K8_REV_E 2
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#define K8_REV_F 4
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/* Hardware limit on ChipSelect rows per MC and processors per system */
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#define MAX_CS_COUNT 8
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#define DRAM_REG_COUNT 8
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#define ON true
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#define OFF false
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/*
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* PCI-defined configuration space registers
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@ -241,7 +239,7 @@
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#define F10_DCHR_1 0x194
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#define F10_DCHR_FOUR_RANK_DIMM BIT(18)
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#define F10_DCHR_Ddr3Mode BIT(8)
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#define DDR3_MODE BIT(8)
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#define F10_DCHR_MblMode BIT(6)
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@ -382,14 +380,9 @@ enum {
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#define K8_NBCAP_CORES (BIT(12)|BIT(13))
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#define K8_NBCAP_CHIPKILL BIT(4)
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#define K8_NBCAP_SECDED BIT(3)
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#define K8_NBCAP_8_NODE BIT(2)
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#define K8_NBCAP_DUAL_NODE BIT(1)
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#define K8_NBCAP_DCT_DUAL BIT(0)
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/*
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* MSR Regs
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*/
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#define K8_MSR_MCGCTL 0x017b
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/* MSRs */
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#define K8_MSR_MCGCTL_NBE BIT(4)
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#define K8_MSR_MC4CTL 0x0410
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@ -487,7 +480,6 @@ struct amd64_pvt {
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/* Save old hw registers' values before we modified them */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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u32 old_nbctl;
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unsigned long old_mcgctl; /* per core on this node */
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/* MC Type Index value: socket F vs Family 10h */
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u32 mc_type_index;
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@ -495,6 +487,7 @@ struct amd64_pvt {
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/* misc settings */
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struct flags {
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unsigned long cf8_extcfg:1;
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unsigned long ecc_report:1;
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} flags;
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};
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@ -504,7 +497,6 @@ struct scrubrate {
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};
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extern struct scrubrate scrubrates[23];
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extern u32 revf_quad_ddr2_shift[16];
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extern const char *tt_msgs[4];
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extern const char *ll_msgs[4];
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extern const char *rrrr_msgs[16];
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@ -534,17 +526,15 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
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* functions and per device encoding/decoding logic.
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*/
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struct low_ops {
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int (*probe_valid_hardware)(struct amd64_pvt *pvt);
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int (*early_channel_count)(struct amd64_pvt *pvt);
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int (*early_channel_count) (struct amd64_pvt *pvt);
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u64 (*get_error_address)(struct mem_ctl_info *mci,
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struct err_regs *info);
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void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
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void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
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struct err_regs *info,
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u64 SystemAddr);
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int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
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u64 (*get_error_address) (struct mem_ctl_info *mci,
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struct err_regs *info);
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void (*read_dram_base_limit) (struct amd64_pvt *pvt, int dram);
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void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
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struct err_regs *info, u64 SystemAddr);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
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};
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struct amd64_family_type {
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@ -566,6 +556,22 @@ static inline struct low_ops *family_ops(int index)
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return &amd64_family_types[index].ops;
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}
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static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 *val, const char *func)
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{
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int err = 0;
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err = pci_read_config_dword(pdev, offset, val);
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if (err)
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amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
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func, PCI_FUNC(pdev->devfn), offset);
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return err;
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}
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#define amd64_read_pci_cfg(pdev, offset, val) \
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amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
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/*
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* For future CPU versions, verify the following as new 'slow' rates appear and
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* modify the necessary skip values for the supported CPU.
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@ -74,6 +74,7 @@
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#ifdef CONFIG_EDAC_DEBUG
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extern int edac_debug_level;
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extern const char *edac_mem_types[];
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#ifndef CONFIG_EDAC_DEBUG_VERBOSE
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#define edac_debug_printk(level, fmt, arg...) \
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@ -76,6 +76,30 @@ static void edac_mc_dump_mci(struct mem_ctl_info *mci)
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debugf3("\tpvt_info = %p\n\n", mci->pvt_info);
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}
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/*
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* keep those in sync with the enum mem_type
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*/
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const char *edac_mem_types[] = {
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"Empty csrow",
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"Reserved csrow type",
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"Unknown csrow type",
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"Fast page mode RAM",
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"Extended data out RAM",
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"Burst Extended data out RAM",
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"Single data rate SDRAM",
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"Registered single data rate SDRAM",
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"Double data rate SDRAM",
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"Registered Double data rate SDRAM",
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"Rambus DRAM",
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"Unbuffered DDR2 RAM",
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"Fully buffered DDR2",
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"Registered DDR2 RAM",
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"Rambus XDR",
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"Unbuffered DDR3 RAM",
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"Registered DDR3 RAM",
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};
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EXPORT_SYMBOL_GPL(edac_mem_types);
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#endif /* CONFIG_EDAC_DEBUG */
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/* 'ptr' points to a possibly unaligned item X such that sizeof(X) is 'size'.
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@ -306,7 +306,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 8)) {
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(boot_cpu_data.x86_model > 7)) {
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if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
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} else {
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