i2c-bfin-twi: Add repeat start feature to avoid break of a bundle of i2c master xfer operation
- Create a new mode TWI_I2C_MODE_REPEAT. - No change to smbus operation. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Sonic Zhang
Jean Delvare
parent
4c03f68fc4
commit
4dd39bb12f
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@ -39,9 +39,10 @@
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#define POLL_TIMEOUT (2 * HZ)
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/* SMBus mode*/
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#define TWI_I2C_MODE_STANDARD 0x01
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#define TWI_I2C_MODE_STANDARDSUB 0x02
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#define TWI_I2C_MODE_COMBINED 0x04
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#define TWI_I2C_MODE_STANDARD 1
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#define TWI_I2C_MODE_STANDARDSUB 2
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#define TWI_I2C_MODE_COMBINED 3
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#define TWI_I2C_MODE_REPEAT 4
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struct bfin_twi_iface {
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int irq;
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@ -58,6 +59,9 @@ struct bfin_twi_iface {
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struct timer_list timeout_timer;
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struct i2c_adapter adap;
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struct completion complete;
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struct i2c_msg *pmsg;
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int msg_num;
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int cur_msg;
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};
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static struct bfin_twi_iface twi_iface;
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@ -76,12 +80,16 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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/* start receive immediately after complete sending in
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* combine mode.
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*/
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else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| MDIR | RSTART);
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} else if (iface->manual_stop)
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else if (iface->manual_stop)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| STOP);
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else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| RSTART);
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SSYNC();
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/* Clear status */
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bfin_write_TWI_INT_STAT(XMTSERV);
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@ -108,6 +116,11 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| STOP);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| RSTART);
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SSYNC();
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}
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/* Clear interrupt source */
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bfin_write_TWI_INT_STAT(RCVSERV);
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@ -119,7 +132,7 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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bfin_write_TWI_MASTER_STAT(0x3e);
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bfin_write_TWI_MASTER_CTL(0);
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SSYNC();
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iface->result = -1;
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iface->result = -EIO;
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/* if both err and complete int stats are set, return proper
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* results.
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*/
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@ -170,6 +183,42 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
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MEN | MDIR);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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iface->cur_msg++;
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iface->transPtr = iface->pmsg[iface->cur_msg].buf;
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iface->writeNum = iface->readNum =
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iface->pmsg[iface->cur_msg].len;
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/* Set Transmit device address */
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bfin_write_TWI_MASTER_ADDR(
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iface->pmsg[iface->cur_msg].addr);
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if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(
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*(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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if (iface->pmsg[iface->cur_msg].len <= 255)
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bfin_write_TWI_MASTER_CTL(
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iface->pmsg[iface->cur_msg].len << 6);
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else {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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}
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/* remove restart bit and enable master receive */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() &
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~RSTART);
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
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MEN | ((iface->read_write == I2C_SMBUS_READ) ?
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MDIR : 0));
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SSYNC();
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} else {
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iface->result = 1;
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bfin_write_TWI_INT_MASK(0);
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@ -221,7 +270,6 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
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{
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struct bfin_twi_iface *iface = adap->algo_data;
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struct i2c_msg *pmsg;
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int i, ret;
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int rc = 0;
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if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
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@ -231,81 +279,76 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
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yield();
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}
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ret = 0;
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for (i = 0; rc >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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if (pmsg->flags & I2C_M_TEN) {
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dev_err(&(adap->dev), "i2c-bfin-twi: 10 bits addr "
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"not supported !\n");
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rc = -EINVAL;
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break;
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}
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iface->pmsg = msgs;
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iface->msg_num = num;
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iface->cur_msg = 0;
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iface->cur_mode = TWI_I2C_MODE_STANDARD;
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iface->manual_stop = 0;
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iface->transPtr = pmsg->buf;
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iface->writeNum = iface->readNum = pmsg->len;
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iface->result = 0;
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iface->timeout_count = 10;
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/* Set Transmit device address */
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bfin_write_TWI_MASTER_ADDR(pmsg->addr);
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/* FIFO Initiation. Data in FIFO should be
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* discarded before start a new operation.
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*/
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bfin_write_TWI_FIFO_CTL(0x3);
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SSYNC();
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bfin_write_TWI_FIFO_CTL(0);
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SSYNC();
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if (pmsg->flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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/* clear int stat */
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bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV);
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/* Interrupt mask . Enable XMT, RCV interrupt */
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bfin_write_TWI_INT_MASK(MCOMP | MERR |
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((iface->read_write == I2C_SMBUS_READ)?
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RCVSERV : XMTSERV));
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SSYNC();
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if (pmsg->len > 0 && pmsg->len <= 255)
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bfin_write_TWI_MASTER_CTL(pmsg->len << 6);
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else if (pmsg->len > 255) {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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} else
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break;
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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/* Master enable */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
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((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
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((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
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SSYNC();
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wait_for_completion(&iface->complete);
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rc = iface->result;
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if (rc == 1)
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ret++;
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else if (rc == -1)
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break;
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pmsg = &msgs[0];
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if (pmsg->flags & I2C_M_TEN) {
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dev_err(&adap->dev, "10 bits addr not supported!\n");
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return -EINVAL;
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}
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return ret;
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iface->cur_mode = TWI_I2C_MODE_REPEAT;
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iface->manual_stop = 0;
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iface->transPtr = pmsg->buf;
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iface->writeNum = iface->readNum = pmsg->len;
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iface->result = 0;
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iface->timeout_count = 10;
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/* Set Transmit device address */
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bfin_write_TWI_MASTER_ADDR(pmsg->addr);
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/* FIFO Initiation. Data in FIFO should be
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* discarded before start a new operation.
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*/
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bfin_write_TWI_FIFO_CTL(0x3);
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SSYNC();
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bfin_write_TWI_FIFO_CTL(0);
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SSYNC();
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if (pmsg->flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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/* clear int stat */
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bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
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/* Interrupt mask . Enable XMT, RCV interrupt */
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bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV);
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SSYNC();
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if (pmsg->len <= 255)
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bfin_write_TWI_MASTER_CTL(pmsg->len << 6);
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else {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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}
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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/* Master enable */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
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((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
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((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
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SSYNC();
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wait_for_completion(&iface->complete);
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rc = iface->result;
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if (rc == 1)
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return num;
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else
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return rc;
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}
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/*
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