viafb: delete clock and PLL initialization
We do this also in the real program code so there is no reason to do it here too (and here it's hardly readable). Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
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bea02e4587
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4d9fd0b72c
1 changed files with 2 additions and 6 deletions
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@ -41,7 +41,6 @@ struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
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{VIACR, CR69, 0xFF, 0x00},
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{VIACR, CR6A, 0xFF, 0x40},
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{VIACR, CR6B, 0xFF, 0x00},
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{VIACR, CR6C, 0xFF, 0x00},
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{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
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{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
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{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
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@ -87,7 +86,6 @@ struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
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{VIACR, CR69, 0xFF, 0x00},
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{VIACR, CR6A, 0xFD, 0x40},
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{VIACR, CR6B, 0xFF, 0x00},
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{VIACR, CR6C, 0xFF, 0x00},
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{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
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{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
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{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
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@ -161,7 +159,7 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
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{VIASR, SR1B, 0xFF, 0xF0},
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{VIASR, SR1E, 0xFF, 0x01},
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{VIASR, SR2A, 0xFF, 0x00},
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{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
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{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
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{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
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{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
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{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
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@ -174,7 +172,6 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
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{VIACR, CR69, 0xFF, 0x00},
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{VIACR, CR6A, 0xFF, 0x40},
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{VIACR, CR6B, 0xFF, 0x00},
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{VIACR, CR6C, 0xFF, 0x00},
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{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
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{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
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{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
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@ -204,7 +201,7 @@ struct io_reg VX855_ModeXregs[] = {
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{VIASR, SR2A, 0xF0, 0x00},
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{VIASR, SR58, 0xFF, 0x00},
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{VIASR, SR59, 0xFF, 0x00},
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{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
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{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
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{VIACR, CR09, 0xFF, 0x00}, /* Initial CR09=0*/
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{VIACR, CR11, 0x8F, 0x00}, /* IGA1 initial Vertical end */
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{VIACR, CR17, 0x7F, 0x00}, /* IGA1 CRT Mode control init */
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@ -219,7 +216,6 @@ struct io_reg VX855_ModeXregs[] = {
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{VIACR, CR69, 0xFF, 0x00},
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{VIACR, CR6A, 0xFD, 0x60},
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{VIACR, CR6B, 0xFF, 0x00},
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{VIACR, CR6C, 0xFF, 0x00},
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{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
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{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
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{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
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