bnx2x: Supporting BCM8727 PHY
Adding support for BCM8727 - a dual port SFP+ PHY. That includes verification of the optic module vendor and part number - the list of approved modules resides on the nvram and the module is verified by the FW. Since not all users would like to use this verification feature, it can be disabled. The default behavior is to issue a warning if the module is not approved, but still allow using it - but it is also possible to disable the link if the module is not approved. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
5316bc0b9a
commit
4d295db0ef
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@ -1006,6 +1006,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
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int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
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int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
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u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
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static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
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int wait)
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@ -248,6 +248,8 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
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@ -358,10 +360,16 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
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#define PORT_FEATURE_MBA_ENABLED 0x02000000
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#define PORT_FEATURE_MFW_ENABLED 0x04000000
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/* Check the optic vendor via i2c before allowing it to be used by
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SW */
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED 0x00000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED 0x08000000
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/* Reserved bits: 28-29 */
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/* Check the optic vendor via i2c against a list of approved modules
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in a separate nvram image */
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
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u32 wol_config;
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/* Default is used when driver sets to "auto" mode */
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@ -657,6 +665,12 @@ struct drv_func_mb {
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#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
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#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
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#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
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/*
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* The optic module verification commands requris bootcode
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* v5.0.6 or later
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*/
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#define DRV_MSG_CODE_VRFY_OPT_MDL 0xa0000000
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#define REQ_BC_VER_4_VRFY_OPT_MDL 0x00050006
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#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
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#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
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@ -691,6 +705,9 @@ struct drv_func_mb {
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#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
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#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
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#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
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#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
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#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
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#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
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#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
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#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
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File diff suppressed because it is too large
Load Diff
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@ -39,7 +39,13 @@
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#define SPEED_15000 15000
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#define SPEED_16000 16000
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#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
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#define SFP_EEPROM_VENDOR_NAME_SIZE 16
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#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
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#define SFP_EEPROM_VENDOR_OUI_SIZE 3
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#define SFP_EEPROM_PART_NO_ADDR 0x28
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#define SFP_EEPROM_PART_NO_SIZE 16
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#define PWR_FLT_ERR_MSG_LEN 250
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/***********************************************************/
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/* Structs */
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/***********************************************************/
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@ -91,7 +97,8 @@ struct link_params {
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u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
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u32 feature_config_flags;
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#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0)
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#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
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#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
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/* Device pointer passed to all callback functions */
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struct bnx2x *bp;
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};
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@ -181,4 +188,7 @@ u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
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u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
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u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
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u8 byte_cnt, u8 *o_buf);
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#endif /* BNX2X_LINK_H */
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@ -2637,7 +2637,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
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{
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int port = BP_PORT(bp);
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int reg_offset;
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u32 val;
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u32 val, swap_val, swap_override;
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reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
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MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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@ -2661,6 +2661,17 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
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MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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/* The PHY reset is controlled by GPIO 1 */
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/* fake the port number to cancel the swap done in
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set_gpio() */
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swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
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swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
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port = (swap_val && swap_override) ^ 1;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
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MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
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break;
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default:
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break;
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}
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@ -5561,6 +5572,8 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
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is_required |=
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((phy_type ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
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(phy_type ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
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(phy_type ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
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}
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@ -5812,6 +5825,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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bp->port.need_hw_lock = 1;
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break;
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@ -6050,10 +6064,15 @@ static int bnx2x_init_port(struct bnx2x *bp)
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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/* add SPIO 5 to group 0 */
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val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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{
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u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
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MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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val = REG_RD(bp, reg_addr);
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val |= AEU_INPUTS_ATTN_BITS_SPIO5;
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REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
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REG_WR(bp, reg_addr, val);
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}
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break;
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default:
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@ -6203,7 +6222,7 @@ init_hw_err:
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}
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/* send the MCP a request, block until there is a reply */
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static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
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u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
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{
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int func = BP_FUNC(bp);
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u32 seq = ++bp->fw_seq;
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@ -7676,6 +7695,9 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
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BNX2X_ERR("This driver needs bc_ver %X but found %X,"
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" please upgrade BC\n", BNX2X_BC_VER, val);
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}
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bp->link_params.feature_config_flags |=
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(val >= REQ_BC_VER_4_VRFY_OPT_MDL) ?
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FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
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if (BP_E1HVN(bp) == 0) {
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pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
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@ -7836,6 +7858,18 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_Autoneg |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
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ext_phy_type);
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@ -8099,6 +8133,17 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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bp->link_params.ext_phy_config =
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SHMEM_RD(bp,
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dev_info.port_hw_config[port].external_phy_config);
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/* BCM8727_NOC => BCM8727 no over current */
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if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
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bp->link_params.ext_phy_config &=
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~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
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bp->link_params.ext_phy_config |=
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
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bp->link_params.feature_config_flags |=
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FEATURE_CONFIG_BCM8727_NOC;
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}
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bp->link_params.speed_cap_mask =
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SHMEM_RD(bp,
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dev_info.port_hw_config[port].speed_capability_mask);
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@ -8119,17 +8164,10 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
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}
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config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
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if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
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bp->link_params.feature_config_flags |=
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FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
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else
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bp->link_params.feature_config_flags &=
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~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
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/* If the device is capable of WoL, set the default state according
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* to the HW
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*/
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config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
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bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
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(config & PORT_FEATURE_WOL_ENABLED));
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@ -8139,8 +8177,8 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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bp->link_params.ext_phy_config,
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bp->link_params.speed_cap_mask, bp->port.link_config);
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bp->link_params.switch_cfg = (bp->port.link_config &
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PORT_FEATURE_CONNECTED_SWITCH_MASK);
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bp->link_params.switch_cfg |= (bp->port.link_config &
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PORT_FEATURE_CONNECTED_SWITCH_MASK);
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bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
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bnx2x_link_settings_requested(bp);
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@ -8336,6 +8374,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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cmd->port = PORT_FIBRE;
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break;
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@ -5845,25 +5845,33 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_PMA_REG_ROM_VER2 0xca1a
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#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
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#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
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#define MDIO_PMA_REG_GEN_CTRL2 0xca1e
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#define MDIO_PMA_REG_PLL_CTRL 0xca1e
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#define MDIO_PMA_REG_MISC_CTRL0 0xca23
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#define MDIO_PMA_REG_LRM_MODE 0xca3f
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#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
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#define MDIO_PMA_REG_MISC_CTRL1 0xca85
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#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000
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#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c
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#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002
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#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003
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#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
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#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
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#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
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#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
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#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
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#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
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#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
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#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
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#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
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#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
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#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
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#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
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#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
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#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
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#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
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#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
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#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
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#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
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#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
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#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
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#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
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#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
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