Merge branch 'next/topic-plat-samsung-1' into next-samsung-cleanup
This commit is contained in:
Kukjin Kim
commit
4c59de052e
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@ -14,9 +14,53 @@
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#define __ASM_ARCH_MAP_H
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#include <plat/map-base.h>
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#include <plat/map.h>
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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/*
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* S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
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* So need to define it, and here is to avoid redefinition warning.
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*/
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#define S3C_UART_OFFSET (0x4000)
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#include <plat/map-s3c.h>
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/*
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* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* UARTs */
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#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
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/* Timers */
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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/* Clock and Power management */
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#define S3C24XX_SZ_CLKPWR SZ_1M
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/* USB Device port */
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#define S3C2410_PA_USBDEV (0x52000000)
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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/* Standard size definitions for peripheral blocks. */
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#define S3C24XX_SZ_UART SZ_1M
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#define S3C24XX_SZ_IIS SZ_1M
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#define S3C24XX_SZ_ADC SZ_1M
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#define S3C24XX_SZ_SPI SZ_1M
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#define S3C24XX_SZ_SDI SZ_1M
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#define S3C24XX_SZ_NAND SZ_1M
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#define S3C24XX_SZ_GPIO SZ_1M
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/* USB host controller */
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#define S3C2410_PA_USBHOST (0x49000000)
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@ -75,10 +119,8 @@
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/* S3C2412 memory and IO controls */
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#define S3C2412_PA_SSMC (0x4F000000)
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#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
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#define S3C2412_PA_EBI (0x48800000)
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#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
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/* physical addresses of all the chip-select areas */
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@ -100,12 +142,10 @@
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#define S3C24XX_PA_DMA S3C2410_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C2410_PA_LCD
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
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#define S3C24XX_PA_IIS S3C2410_PA_IIS
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#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
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#define S3C24XX_PA_RTC S3C2410_PA_RTC
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#define S3C24XX_PA_ADC S3C2410_PA_ADC
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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@ -16,6 +16,7 @@
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#define __ASM_ARCH_MAP_H __FILE__
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#include <plat/map-base.h>
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#include <plat/map-s3c.h>
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/*
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* Post-mux Chip Select Regions Xm0CSn_
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@ -83,7 +84,6 @@
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#define S3C64XX_PA_IIC1 (0x7F00F000)
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#define S3C64XX_PA_GPIO (0x7F008000)
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#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
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#define S3C64XX_SZ_GPIO SZ_4K
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#define S3C64XX_PA_SDRAM (0x50000000)
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@ -94,16 +94,10 @@
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#define S3C64XX_PA_VIC1 (0x71300000)
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#define S3C64XX_PA_MODEM (0x74108000)
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#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
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#define S3C64XX_PA_USBHOST (0x74300000)
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#define S3C64XX_PA_USB_HSPHY (0x7C100000)
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#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
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/* place VICs close together */
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#define VA_VIC0 (S3C_VA_IRQ + 0x00)
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#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
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/* compatibiltiy defines. */
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#define S3C_PA_TIMER S3C64XX_PA_TIMER
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@ -119,7 +113,6 @@
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#define S3C_PA_FB S3C64XX_PA_FB
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#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
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#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
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#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
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#define S3C_PA_RTC S3C64XX_PA_RTC
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#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
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@ -1,100 +0,0 @@
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/* linux/include/asm-arm/plat-s3c24xx/map.h
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*
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* Copyright (c) 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S3C24XX_MAP_H
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#define __ASM_PLAT_S3C24XX_MAP_H
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/* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* UARTs */
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#define S3C24XX_VA_UART S3C_VA_UART
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_SZ_UART SZ_1M
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#define S3C_UART_OFFSET (0x4000)
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#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
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/* Timers */
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#define S3C24XX_VA_TIMER S3C_VA_TIMER
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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/* Clock and Power management */
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#define S3C24XX_VA_CLKPWR S3C_VA_SYS
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#define S3C24XX_SZ_CLKPWR SZ_1M
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/* USB Device port */
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#define S3C2410_PA_USBDEV (0x52000000)
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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/* Standard size definitions for peripheral blocks. */
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#define S3C24XX_SZ_IIS SZ_1M
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#define S3C24XX_SZ_ADC SZ_1M
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#define S3C24XX_SZ_SPI SZ_1M
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#define S3C24XX_SZ_SDI SZ_1M
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#define S3C24XX_SZ_NAND SZ_1M
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/* GPIO ports */
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/* the calculation for the VA of this must ensure that
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 mapping. This puts it (currently) at
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* 0xFA800000, which is not in the way of any current mapping
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* by the base system.
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*/
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#define S3C2410_PA_GPIO (0x56000000)
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#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
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#define S3C24XX_SZ_GPIO SZ_1M
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/* ISA style IO, for each machine to sort out mappings for, if it
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* implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#endif /* __ASM_PLAT_S3C24XX_MAP_H */
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@ -0,0 +1,84 @@
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/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h
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*
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* Copyright (c) 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_MAP_S3C_H
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#define __ASM_PLAT_MAP_S3C_H __FILE__
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C24XX_VA_UART S3C_VA_UART
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#define S3C24XX_VA_TIMER S3C_VA_TIMER
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#define S3C24XX_VA_CLKPWR S3C_VA_SYS
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#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
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#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
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#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#ifndef S3C_UART_OFFSET
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#define S3C_UART_OFFSET (0x400)
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#endif
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/*
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* GPIO ports
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*
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* the calculation for the VA of this must ensure that
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 mapping. This puts it (currently) at
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* 0xFA800000, which is not in the way of any current mapping
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* by the base system.
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*/
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#define S3C2410_PA_GPIO (0x56000000)
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#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
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#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
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#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
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#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
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#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
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#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
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/*
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* ISA style IO, for each machine to sort out mappings for,
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* if it implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#include <plat/map-s5p.h>
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#endif /* __ASM_PLAT_MAP_S3C_H */
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h
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/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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@ -40,8 +40,6 @@
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#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
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#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
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#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
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#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
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#define VA_VIC0 VA_VIC(0)
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#define VA_VIC1 VA_VIC(1)
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@ -58,4 +56,6 @@
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#define S3C_UART_OFFSET (0x400)
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#endif
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#include <plat/map-s3c.h>
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#endif /* __ASM_PLAT_MAP_S5P_H */
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Reference in New Issue