Staging: et131x: clean up the pkt_desc_stat_t types
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
8a66278cf9
commit
4ba64c1ba5
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@ -193,7 +193,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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&rx_ring->Fbr1Realpa,
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&rx_ring->Fbr1offset, 0x0FFF);
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rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa +
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rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa +
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rx_ring->Fbr1offset);
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#ifdef USE_FBR0
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@ -222,7 +222,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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&rx_ring->Fbr0Realpa,
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&rx_ring->Fbr0offset, 0x0FFF);
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rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa +
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rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa +
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rx_ring->Fbr0offset);
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#endif
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@ -270,7 +270,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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* access later
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*/
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rx_ring->fbr[1]->virt[index] =
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(uint8_t *) rx_ring->Fbr1MemVa[i] +
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(u8 *) rx_ring->Fbr1MemVa[i] +
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(j * rx_ring->Fbr1BufferSize) + Fbr1Offset;
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/* now store the physical address in the descriptor
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@ -319,7 +319,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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u32 index = (i * FBR_CHUNKS) + j;
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rx_ring->fbr[0]->virt[index] =
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(uint8_t *) rx_ring->Fbr0MemVa[i] +
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(u8 *) rx_ring->Fbr0MemVa[i] +
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(j * rx_ring->Fbr0BufferSize) + Fbr0Offset;
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rx_ring->fbr[0]->bus_high[index] =
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@ -338,7 +338,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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/* Allocate an area of memory for FIFO of Packet Status ring entries */
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pktStatRingSize =
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sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
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sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries;
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rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
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pktStatRingSize,
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@ -446,7 +446,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
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}
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/* Now the FIFO itself */
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rx_ring->pFbr1RingVa = (void *)((uint8_t *)
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rx_ring->pFbr1RingVa = (void *)((u8 *)
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rx_ring->pFbr1RingVa - rx_ring->Fbr1offset);
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bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries)
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@ -479,7 +479,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
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}
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/* Now the FIFO itself */
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rx_ring->pFbr0RingVa = (void *)((uint8_t *)
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rx_ring->pFbr0RingVa = (void *)((u8 *)
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rx_ring->pFbr0RingVa - rx_ring->Fbr0offset);
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bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries)
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@ -496,7 +496,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
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/* Free Packet Status Ring */
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if (rx_ring->pPSRingVa) {
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pktStatRingSize =
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sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
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sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries;
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pci_free_consistent(adapter->pdev, pktStatRingSize,
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rx_ring->pPSRingVa, rx_ring->pPSRingPa);
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@ -785,16 +785,16 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
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{
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struct _rx_ring_t *rx_local = &etdev->RxRing;
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struct rx_status_block *status;
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PPKT_STAT_DESC_t psr;
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struct pkt_stat_desc *psr;
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PMP_RFD rfd;
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u32 i;
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uint8_t *buf;
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u8 *buf;
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unsigned long flags;
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struct list_head *element;
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uint8_t rindex;
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uint16_t bindex;
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u8 rindex;
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u16 bindex;
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u32 len;
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PKT_STAT_DESC_WORD0_t Word0;
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u32 word0;
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u32 word1;
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/* RX Status block is written by the DMA engine prior to every
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@ -810,17 +810,17 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
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return NULL;
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/* The packet status ring indicates that data is available. */
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psr = (PPKT_STAT_DESC_t) (rx_local->pPSRingVa) +
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psr = (struct pkt_stat_desc *) (rx_local->pPSRingVa) +
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(rx_local->local_psr_full & 0xFFF);
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/* Grab any information that is required once the PSR is
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* advanced, since we can no longer rely on the memory being
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* accurate
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*/
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len = psr->word1.bits.length;
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rindex = (uint8_t) psr->word1.bits.ri;
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bindex = (uint16_t) psr->word1.bits.bi;
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Word0 = psr->word0;
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len = psr->word1 & 0xFFFF;
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rindex = (psr->word1 >> 26) & 0x03;
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bindex = (psr->word1 >> 16) & 0x3FF;
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word0 = psr->word0;
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/* Indicate that we have used this PSR entry. */
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/* FIXME wrap 12 */
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@ -835,9 +835,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
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&etdev->regs->rxdma.psr_full_offset);
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#ifndef USE_FBR0
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if (rindex != 1) {
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if (rindex != 1)
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return NULL;
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}
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#endif
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#ifdef USE_FBR0
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@ -904,8 +903,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
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}
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/* Determine if this is a multicast packet coming in */
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if ((Word0.value & ALCATEL_MULTICAST_PKT) &&
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!(Word0.value & ALCATEL_BROADCAST_PKT)) {
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if ((word0 & ALCATEL_MULTICAST_PKT) &&
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!(word0 & ALCATEL_BROADCAST_PKT)) {
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/* Promiscuous mode and Multicast mode are
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* not mutually exclusive as was first
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* thought. I guess Promiscuous is just
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@ -956,7 +955,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
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if (len > 0)
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etdev->Stats.multircv++;
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} else if (Word0.value & ALCATEL_BROADCAST_PKT)
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} else if (word0 & ALCATEL_BROADCAST_PKT)
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etdev->Stats.brdcstrcv++;
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else
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/* Not sure what this counter measures in
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@ -1094,8 +1093,8 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd)
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{
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struct _rx_ring_t *rx_local = &etdev->RxRing;
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struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma;
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uint16_t bi = rfd->bufferindex;
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uint8_t ri = rfd->ringindex;
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u16 bi = rfd->bufferindex;
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u8 ri = rfd->ringindex;
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unsigned long flags;
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/* We don't use any of the OOB data besides status. Otherwise, we
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@ -98,101 +98,53 @@ struct fbr_desc
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u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
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};
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/* Typedefs for Packet Status Ring Descriptors */
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typedef union _PKT_STAT_DESC_WORD0_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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/* top 16 bits are from the Alcatel Status Word as enumerated in */
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/* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */
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#if 0
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u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
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#endif
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u32 asw_long_evt:1; /* bit 31(Rx long event) */
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u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
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u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
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u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
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u32 asw_control_frame:1; /* bit 27(is a control frame) */
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u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
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u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
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u32 asw_multicast:1; /* bit 24(has a multicast address) */
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u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
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u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
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u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
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u32 asw_CRC_err:1; /* bit 20(CRC error) */
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u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
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u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
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u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
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u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
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u32 unused:5; /* bits 11-15 */
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u32 vp:1; /* bit 10(VLAN Packet) */
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u32 jp:1; /* bit 9(Jumbo Packet) */
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u32 ft:1; /* bit 8(Frame Truncated) */
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u32 drop:1; /* bit 7(Drop packet) */
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u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
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u32 wol:1; /* bit 5(WOL Event) */
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u32 tcpp:1; /* bit 4(TCP checksum pass) */
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u32 tcpa:1; /* bit 3(TCP checksum assist) */
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u32 ipp:1; /* bit 2(IP checksum pass) */
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u32 ipa:1; /* bit 1(IP checksum assist) */
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u32 hp:1; /* bit 0(hash pass) */
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#else
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u32 hp:1; /* bit 0(hash pass) */
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u32 ipa:1; /* bit 1(IP checksum assist) */
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u32 ipp:1; /* bit 2(IP checksum pass) */
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u32 tcpa:1; /* bit 3(TCP checksum assist) */
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u32 tcpp:1; /* bit 4(TCP checksum pass) */
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u32 wol:1; /* bit 5(WOL Event) */
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u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
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u32 drop:1; /* bit 7(Drop packet) */
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u32 ft:1; /* bit 8(Frame Truncated) */
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u32 jp:1; /* bit 9(Jumbo Packet) */
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u32 vp:1; /* bit 10(VLAN Packet) */
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u32 unused:5; /* bits 11-15 */
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u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
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u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
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u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
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u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
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u32 asw_CRC_err:1; /* bit 20(CRC error) */
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u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
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u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
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u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
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u32 asw_multicast:1; /* bit 24(has a multicast address) */
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u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
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u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
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u32 asw_control_frame:1; /* bit 27(is a control frame) */
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u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
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u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
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u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
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u32 asw_long_evt:1; /* bit 31(Rx long event) */
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#if 0
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u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
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#endif
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#endif
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} bits;
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} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
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/* Packet Status Ring Descriptors
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*
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* Word 0:
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*
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* top 16 bits are from the Alcatel Status Word as enumerated in
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* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
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*
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* 0: hp hash pass
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* 1: ipa IP checksum assist
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* 2: ipp IP checksum pass
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* 3: tcpa TCP checksum assist
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* 4: tcpp TCP checksum pass
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* 5: wol WOL Event
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* 6: rxmac_error RXMAC Error Indicator
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* 7: drop Drop packet
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* 8: ft Frame Truncated
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* 9: jp Jumbo Packet
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* 10: vp VLAN Packet
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* 11-15: unused
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* 16: asw_prev_pkt_dropped e.g. IFG too small on previous
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* 17: asw_RX_DV_event short receive event detected
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* 18: asw_false_carrier_event bad carrier since last good packet
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* 19: asw_code_err one or more nibbles signalled as errors
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* 20: asw_CRC_err CRC error
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* 21: asw_len_chk_err frame length field incorrect
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* 22: asw_too_long frame length > 1518 bytes
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* 23: asw_OK valid CRC + no code error
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* 24: asw_multicast has a multicast address
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* 25: asw_broadcast has a broadcast address
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* 26: asw_dribble_nibble spurious bits after EOP
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* 27: asw_control_frame is a control frame
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* 28: asw_pause_frame is a pause frame
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* 29: asw_unsupported_op unsupported OP code
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* 30: asw_VLAN_tag VLAN tag detected
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* 31: asw_long_evt Rx long event
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*
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* Word 1:
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* 0-15: length length in bytes
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* 16-25: bi Buffer Index
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* 26-27: ri Ring Index
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* 28-31: reserved
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*/
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typedef union _PKT_STAT_DESC_WORD1_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:4; /* bits 28-31 */
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u32 ri:2; /* bits 26-27(Ring Index) */
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u32 bi:10; /* bits 16-25(Buffer Index) */
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u32 length:16; /* bit 0-15(length in bytes) */
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#else
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u32 length:16; /* bit 0-15(length in bytes) */
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u32 bi:10; /* bits 16-25(Buffer Index) */
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u32 ri:2; /* bits 26-27(Ring Index) */
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u32 unused:4; /* bits 28-31 */
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#endif
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} bits;
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} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
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typedef struct _PKT_STAT_DESC_t {
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PKT_STAT_DESC_WORD0_t word0;
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PKT_STAT_DESC_WORD1_t word1;
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} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
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struct pkt_stat_desc {
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u32 word0;
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u32 word1;
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};
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/* Typedefs for the RX DMA status word */
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