sfc: Export boot configuration in EEPROM through ethtool
Extend the SPI device setup code to support this. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
parent
4d566063a7
commit
4a5b504d0c
5 changed files with 445 additions and 94 deletions
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@ -17,6 +17,7 @@
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#include "ethtool.h"
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#include "falcon.h"
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#include "gmii.h"
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#include "spi.h"
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#include "mac.h"
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const char *efx_loopback_mode_names[] = {
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@ -171,6 +172,11 @@ static struct efx_ethtool_stat efx_ethtool_stats[] = {
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/* Number of ethtool statistics */
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#define EFX_ETHTOOL_NUM_STATS ARRAY_SIZE(efx_ethtool_stats)
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/* EEPROM range with gPXE configuration */
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#define EFX_ETHTOOL_EEPROM_MAGIC 0xEFAB
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#define EFX_ETHTOOL_EEPROM_MIN 0x100U
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#define EFX_ETHTOOL_EEPROM_MAX 0x400U
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/**************************************************************************
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*
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* Ethtool operations
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@ -532,6 +538,49 @@ static u32 efx_ethtool_get_link(struct net_device *net_dev)
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return efx->link_up;
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}
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static int efx_ethtool_get_eeprom_len(struct net_device *net_dev)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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struct efx_spi_device *spi = efx->spi_eeprom;
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if (!spi)
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return 0;
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return min(spi->size, EFX_ETHTOOL_EEPROM_MAX) -
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min(spi->size, EFX_ETHTOOL_EEPROM_MIN);
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}
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static int efx_ethtool_get_eeprom(struct net_device *net_dev,
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struct ethtool_eeprom *eeprom, u8 *buf)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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struct efx_spi_device *spi = efx->spi_eeprom;
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size_t len;
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int rc;
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rc = falcon_spi_read(spi, eeprom->offset + EFX_ETHTOOL_EEPROM_MIN,
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eeprom->len, &len, buf);
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eeprom->magic = EFX_ETHTOOL_EEPROM_MAGIC;
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eeprom->len = len;
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return rc;
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}
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static int efx_ethtool_set_eeprom(struct net_device *net_dev,
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struct ethtool_eeprom *eeprom, u8 *buf)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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struct efx_spi_device *spi = efx->spi_eeprom;
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size_t len;
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int rc;
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if (eeprom->magic != EFX_ETHTOOL_EEPROM_MAGIC)
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return -EINVAL;
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rc = falcon_spi_write(spi, eeprom->offset + EFX_ETHTOOL_EEPROM_MIN,
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eeprom->len, &len, buf);
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eeprom->len = len;
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return rc;
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}
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static int efx_ethtool_get_coalesce(struct net_device *net_dev,
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struct ethtool_coalesce *coalesce)
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{
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@ -653,6 +702,9 @@ struct ethtool_ops efx_ethtool_ops = {
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.get_drvinfo = efx_ethtool_get_drvinfo,
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.nway_reset = efx_ethtool_nway_reset,
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.get_link = efx_ethtool_get_link,
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.get_eeprom_len = efx_ethtool_get_eeprom_len,
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.get_eeprom = efx_ethtool_get_eeprom,
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.set_eeprom = efx_ethtool_set_eeprom,
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.get_coalesce = efx_ethtool_get_coalesce,
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.set_coalesce = efx_ethtool_set_coalesce,
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.get_pauseparam = efx_ethtool_get_pauseparam,
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@ -1620,64 +1620,195 @@ void falcon_fini_interrupt(struct efx_nic *efx)
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/* Wait for SPI command completion */
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static int falcon_spi_wait(struct efx_nic *efx)
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{
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unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
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efx_oword_t reg;
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int cmd_en, timer_active;
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int count;
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bool cmd_en, timer_active;
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count = 0;
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do {
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for (;;) {
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falcon_read(efx, ®, EE_SPI_HCMD_REG_KER);
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cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
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timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
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if (!cmd_en && !timer_active)
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return 0;
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udelay(10);
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} while (++count < 10000); /* wait upto 100msec */
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EFX_ERR(efx, "timed out waiting for SPI\n");
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return -ETIMEDOUT;
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if (time_after_eq(jiffies, timeout)) {
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EFX_ERR(efx, "timed out waiting for SPI\n");
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return -ETIMEDOUT;
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}
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cpu_relax();
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}
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}
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static int
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falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
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unsigned int address, unsigned int addr_len,
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void *data, unsigned int len)
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static int falcon_spi_cmd(const struct efx_spi_device *spi,
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unsigned int command, int address,
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const void *in, void *out, unsigned int len)
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{
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struct efx_nic *efx = spi->efx;
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bool addressed = (address >= 0);
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bool reading = (out != NULL);
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efx_oword_t reg;
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int rc;
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BUG_ON(len > FALCON_SPI_MAX_LEN);
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/* Input validation */
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if (len > FALCON_SPI_MAX_LEN)
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return -EINVAL;
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/* Check SPI not currently being accessed */
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rc = falcon_spi_wait(efx);
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if (rc)
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return rc;
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/* Program address register */
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EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
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falcon_write(efx, ®, EE_SPI_HADR_REG_KER);
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/* Program address register, if we have an address */
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if (addressed) {
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EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
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falcon_write(efx, ®, EE_SPI_HADR_REG_KER);
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}
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/* Issue read command */
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/* Program data register, if we have data */
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if (in != NULL) {
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memcpy(®, in, len);
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falcon_write(efx, ®, EE_SPI_HDATA_REG_KER);
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}
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/* Issue read/write command */
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EFX_POPULATE_OWORD_7(reg,
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EE_SPI_HCMD_CMD_EN, 1,
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EE_SPI_HCMD_SF_SEL, device_id,
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EE_SPI_HCMD_SF_SEL, spi->device_id,
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EE_SPI_HCMD_DABCNT, len,
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EE_SPI_HCMD_READ, EE_SPI_READ,
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EE_SPI_HCMD_READ, reading,
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EE_SPI_HCMD_DUBCNT, 0,
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EE_SPI_HCMD_ADBCNT, addr_len,
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EE_SPI_HCMD_ADBCNT,
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(addressed ? spi->addr_len : 0),
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EE_SPI_HCMD_ENC, command);
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falcon_write(efx, ®, EE_SPI_HCMD_REG_KER);
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/* Wait for read to complete */
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/* Wait for read/write to complete */
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rc = falcon_spi_wait(efx);
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if (rc)
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return rc;
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/* Read data */
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falcon_read(efx, ®, EE_SPI_HDATA_REG_KER);
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memcpy(data, ®, len);
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if (out != NULL) {
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falcon_read(efx, ®, EE_SPI_HDATA_REG_KER);
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memcpy(out, ®, len);
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}
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return 0;
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}
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static unsigned int
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falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
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{
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return min(FALCON_SPI_MAX_LEN,
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(spi->block_size - (start & (spi->block_size - 1))));
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}
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static inline u8
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efx_spi_munge_command(const struct efx_spi_device *spi,
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const u8 command, const unsigned int address)
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{
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return command | (((address >> 8) & spi->munge_address) << 3);
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}
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static int falcon_spi_fast_wait(const struct efx_spi_device *spi)
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{
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u8 status;
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int i, rc;
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/* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
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for (i = 0; i < 50; i++) {
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udelay(20);
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rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
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&status, sizeof(status));
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if (rc)
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return rc;
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if (!(status & SPI_STATUS_NRDY))
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return 0;
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}
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EFX_ERR(spi->efx,
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"timed out waiting for device %d last status=0x%02x\n",
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spi->device_id, status);
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return -ETIMEDOUT;
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}
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int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
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size_t len, size_t *retlen, u8 *buffer)
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{
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unsigned int command, block_len, pos = 0;
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int rc = 0;
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while (pos < len) {
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block_len = min((unsigned int)len - pos,
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FALCON_SPI_MAX_LEN);
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command = efx_spi_munge_command(spi, SPI_READ, start + pos);
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rc = falcon_spi_cmd(spi, command, start + pos, NULL,
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buffer + pos, block_len);
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if (rc)
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break;
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pos += block_len;
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/* Avoid locking up the system */
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cond_resched();
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if (signal_pending(current)) {
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rc = -EINTR;
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break;
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}
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}
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if (retlen)
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*retlen = pos;
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return rc;
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}
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int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
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size_t len, size_t *retlen, const u8 *buffer)
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{
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u8 verify_buffer[FALCON_SPI_MAX_LEN];
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unsigned int command, block_len, pos = 0;
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int rc = 0;
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while (pos < len) {
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rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
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if (rc)
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break;
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block_len = min((unsigned int)len - pos,
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falcon_spi_write_limit(spi, start + pos));
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command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
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rc = falcon_spi_cmd(spi, command, start + pos,
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buffer + pos, NULL, block_len);
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if (rc)
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break;
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rc = falcon_spi_fast_wait(spi);
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if (rc)
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break;
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command = efx_spi_munge_command(spi, SPI_READ, start + pos);
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rc = falcon_spi_cmd(spi, command, start + pos,
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NULL, verify_buffer, block_len);
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if (memcmp(verify_buffer, buffer + pos, block_len)) {
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rc = -EIO;
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break;
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}
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pos += block_len;
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/* Avoid locking up the system */
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cond_resched();
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if (signal_pending(current)) {
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rc = -EINTR;
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break;
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}
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}
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if (retlen)
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*retlen = pos;
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return rc;
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}
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/**************************************************************************
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*
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* MAC wrapper
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@ -2251,40 +2382,66 @@ static int falcon_reset_sram(struct efx_nic *efx)
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return -ETIMEDOUT;
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}
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static int falcon_spi_device_init(struct efx_nic *efx,
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struct efx_spi_device **spi_device_ret,
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unsigned int device_id, u32 device_type)
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{
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struct efx_spi_device *spi_device;
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if (device_type != 0) {
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spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
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if (!spi_device)
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return -ENOMEM;
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spi_device->device_id = device_id;
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spi_device->size =
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1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
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spi_device->addr_len =
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SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
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spi_device->munge_address = (spi_device->size == 1 << 9 &&
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spi_device->addr_len == 1);
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spi_device->block_size =
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1 << SPI_DEV_TYPE_FIELD(device_type,
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SPI_DEV_TYPE_BLOCK_SIZE);
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spi_device->efx = efx;
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} else {
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spi_device = NULL;
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}
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kfree(*spi_device_ret);
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*spi_device_ret = spi_device;
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return 0;
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}
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static void falcon_remove_spi_devices(struct efx_nic *efx)
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{
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kfree(efx->spi_eeprom);
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efx->spi_eeprom = NULL;
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kfree(efx->spi_flash);
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efx->spi_flash = NULL;
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}
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/* Extract non-volatile configuration */
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static int falcon_probe_nvconfig(struct efx_nic *efx)
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{
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struct falcon_nvconfig *nvconfig;
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efx_oword_t nic_stat;
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int device_id;
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unsigned addr_len;
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size_t offset, len;
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struct efx_spi_device *spi;
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int magic_num, struct_ver, board_rev;
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int rc;
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/* Find the boot device. */
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falcon_read(efx, &nic_stat, NIC_STAT_REG);
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if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
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device_id = EE_SPI_FLASH;
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addr_len = 3;
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} else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
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device_id = EE_SPI_EEPROM;
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addr_len = 2;
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} else {
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return -ENODEV;
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}
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nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
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if (!nvconfig)
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return -ENOMEM;
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/* Read the whole configuration structure into memory. */
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for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
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len = min(sizeof(*nvconfig) - offset,
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(size_t) FALCON_SPI_MAX_LEN);
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rc = falcon_spi_read(efx, device_id, SPI_READ,
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NVCONFIG_BASE + offset, addr_len,
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(char *)nvconfig + offset, len);
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if (rc)
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goto out;
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spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
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rc = falcon_spi_read(spi, NVCONFIG_BASE, sizeof(*nvconfig),
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NULL, (char *)nvconfig);
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if (rc) {
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EFX_ERR(efx, "Failed to read %s\n", efx->spi_flash ? "flash" :
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"EEPROM");
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goto fail1;
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}
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/* Read the MAC addresses */
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@ -2302,17 +2459,38 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
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board_rev = 0;
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} else {
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struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
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struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
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efx->phy_type = v2->port0_phy_type;
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efx->mii.phy_id = v2->port0_phy_addr;
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board_rev = le16_to_cpu(v2->board_revision);
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if (struct_ver >= 3) {
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__le32 fl = v3->spi_device_type[EE_SPI_FLASH];
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__le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
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rc = falcon_spi_device_init(efx, &efx->spi_flash,
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EE_SPI_FLASH,
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le32_to_cpu(fl));
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if (rc)
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goto fail2;
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rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
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EE_SPI_EEPROM,
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le32_to_cpu(ee));
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if (rc)
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goto fail2;
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}
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}
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EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
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efx_set_board_info(efx, board_rev);
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out:
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kfree(nvconfig);
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return 0;
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fail2:
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falcon_remove_spi_devices(efx);
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fail1:
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kfree(nvconfig);
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return rc;
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}
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@ -2363,6 +2541,86 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
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return 0;
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}
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/* Probe all SPI devices on the NIC */
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static void falcon_probe_spi_devices(struct efx_nic *efx)
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{
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efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
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bool has_flash, has_eeprom, boot_is_external;
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falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
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falcon_read(efx, &nic_stat, NIC_STAT_REG);
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falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
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has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
|
||||
has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
|
||||
boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
|
||||
|
||||
if (has_flash) {
|
||||
/* Default flash SPI device: Atmel AT25F1024
|
||||
* 128 KB, 24-bit address, 32 KB erase block,
|
||||
* 256 B write block
|
||||
*/
|
||||
u32 flash_device_type =
|
||||
(17 << SPI_DEV_TYPE_SIZE_LBN)
|
||||
| (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
|
||||
| (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
|
||||
| (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
|
||||
| (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
|
||||
|
||||
falcon_spi_device_init(efx, &efx->spi_flash,
|
||||
EE_SPI_FLASH, flash_device_type);
|
||||
|
||||
if (!boot_is_external) {
|
||||
/* Disable VPD and set clock dividers to safe
|
||||
* values for initial programming.
|
||||
*/
|
||||
EFX_LOG(efx, "Booted from internal ASIC settings;"
|
||||
" setting SPI config\n");
|
||||
EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
|
||||
/* 125 MHz / 7 ~= 20 MHz */
|
||||
EE_SF_CLOCK_DIV, 7,
|
||||
/* 125 MHz / 63 ~= 2 MHz */
|
||||
EE_EE_CLOCK_DIV, 63);
|
||||
falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
|
||||
}
|
||||
}
|
||||
|
||||
if (has_eeprom) {
|
||||
u32 eeprom_device_type;
|
||||
|
||||
/* If it has no flash, it must have a large EEPROM
|
||||
* for chip config; otherwise check whether 9-bit
|
||||
* addressing is used for VPD configuration
|
||||
*/
|
||||
if (has_flash &&
|
||||
(!boot_is_external ||
|
||||
EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
|
||||
/* Default SPI device: Atmel AT25040 or similar
|
||||
* 512 B, 9-bit address, 8 B write block
|
||||
*/
|
||||
eeprom_device_type =
|
||||
(9 << SPI_DEV_TYPE_SIZE_LBN)
|
||||
| (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
|
||||
| (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
|
||||
} else {
|
||||
/* "Large" SPI device: Atmel AT25640 or similar
|
||||
* 8 KB, 16-bit address, 32 B write block
|
||||
*/
|
||||
eeprom_device_type =
|
||||
(13 << SPI_DEV_TYPE_SIZE_LBN)
|
||||
| (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
|
||||
| (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
|
||||
}
|
||||
|
||||
falcon_spi_device_init(efx, &efx->spi_eeprom,
|
||||
EE_SPI_EEPROM, eeprom_device_type);
|
||||
}
|
||||
|
||||
EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
|
||||
(has_flash ? "present" : "absent"),
|
||||
(has_eeprom ? "present" : "absent"));
|
||||
}
|
||||
|
||||
int falcon_probe_nic(struct efx_nic *efx)
|
||||
{
|
||||
struct falcon_nic_data *nic_data;
|
||||
|
@ -2413,6 +2671,8 @@ int falcon_probe_nic(struct efx_nic *efx)
|
|||
(unsigned long long)efx->irq_status.dma_addr,
|
||||
efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
|
||||
|
||||
falcon_probe_spi_devices(efx);
|
||||
|
||||
/* Read in the non-volatile configuration */
|
||||
rc = falcon_probe_nvconfig(efx);
|
||||
if (rc)
|
||||
|
@ -2432,6 +2692,7 @@ int falcon_probe_nic(struct efx_nic *efx)
|
|||
return 0;
|
||||
|
||||
fail5:
|
||||
falcon_remove_spi_devices(efx);
|
||||
falcon_free_buffer(efx, &efx->irq_status);
|
||||
fail4:
|
||||
fail3:
|
||||
|
@ -2608,6 +2869,7 @@ void falcon_remove_nic(struct efx_nic *efx)
|
|||
rc = i2c_del_adapter(&efx->i2c_adap);
|
||||
BUG_ON(rc);
|
||||
|
||||
falcon_remove_spi_devices(efx);
|
||||
falcon_free_buffer(efx, &efx->irq_status);
|
||||
|
||||
falcon_reset_hw(efx, RESET_TYPE_ALL);
|
||||
|
|
|
@ -92,6 +92,17 @@
|
|||
/* SPI host data register */
|
||||
#define EE_SPI_HDATA_REG_KER 0x0120
|
||||
|
||||
/* SPI/VPD config register */
|
||||
#define EE_VPD_CFG_REG_KER 0x0140
|
||||
#define EE_VPD_EN_LBN 0
|
||||
#define EE_VPD_EN_WIDTH 1
|
||||
#define EE_VPD_EN_AD9_MODE_LBN 1
|
||||
#define EE_VPD_EN_AD9_MODE_WIDTH 1
|
||||
#define EE_EE_CLOCK_DIV_LBN 112
|
||||
#define EE_EE_CLOCK_DIV_WIDTH 7
|
||||
#define EE_SF_CLOCK_DIV_LBN 120
|
||||
#define EE_SF_CLOCK_DIV_WIDTH 7
|
||||
|
||||
/* PCIE CORE ACCESS REG */
|
||||
#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68
|
||||
#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70
|
||||
|
@ -115,6 +126,9 @@
|
|||
#define STRAP_PCIE_LBN 0
|
||||
#define STRAP_PCIE_WIDTH 1
|
||||
|
||||
#define BOOTED_USING_NVDEVICE_LBN 3
|
||||
#define BOOTED_USING_NVDEVICE_WIDTH 1
|
||||
|
||||
/* GPIO control register */
|
||||
#define GPIO_CTL_REG_KER 0x0210
|
||||
#define GPIO_OUTPUTS_LBN (16)
|
||||
|
@ -1127,6 +1141,25 @@ struct falcon_nvconfig_board_v2 {
|
|||
__le16 board_revision;
|
||||
} __packed;
|
||||
|
||||
/* Board configuration v3 extra information */
|
||||
struct falcon_nvconfig_board_v3 {
|
||||
__le32 spi_device_type[2];
|
||||
} __packed;
|
||||
|
||||
/* Bit numbers for spi_device_type */
|
||||
#define SPI_DEV_TYPE_SIZE_LBN 0
|
||||
#define SPI_DEV_TYPE_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
|
||||
#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
|
||||
#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
|
||||
#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
|
||||
#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
|
||||
#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
|
||||
#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
|
||||
#define SPI_DEV_TYPE_FIELD(type, field) \
|
||||
(((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(field))
|
||||
|
||||
#define NVCONFIG_BASE 0x300
|
||||
#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
|
||||
struct falcon_nvconfig {
|
||||
|
@ -1144,6 +1177,8 @@ struct falcon_nvconfig {
|
|||
__le16 board_struct_ver;
|
||||
__le16 board_checksum;
|
||||
struct falcon_nvconfig_board_v2 board_v2;
|
||||
efx_oword_t ee_base_page_reg; /* 0x3B0 */
|
||||
struct falcon_nvconfig_board_v3 board_v3;
|
||||
} __packed;
|
||||
|
||||
#endif /* EFX_FALCON_HWDEFS_H */
|
||||
|
|
|
@ -638,6 +638,10 @@ union efx_multicast_hash {
|
|||
* This register is written with the SMP processor ID whenever an
|
||||
* interrupt is handled. It is used by falcon_test_interrupt()
|
||||
* to verify that an interrupt has occurred.
|
||||
* @spi_flash: SPI flash device
|
||||
* This field will be %NULL if no flash device is present.
|
||||
* @spi_eeprom: SPI EEPROM device
|
||||
* This field will be %NULL if no EEPROM device is present.
|
||||
* @n_rx_nodesc_drop_cnt: RX no descriptor drop count
|
||||
* @nic_data: Hardware dependant state
|
||||
* @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
|
||||
|
@ -709,6 +713,9 @@ struct efx_nic {
|
|||
struct efx_buffer irq_status;
|
||||
volatile signed int last_irq_cpu;
|
||||
|
||||
struct efx_spi_device *spi_flash;
|
||||
struct efx_spi_device *spi_eeprom;
|
||||
|
||||
unsigned n_rx_nodesc_drop_cnt;
|
||||
|
||||
struct falcon_nic_data *nic_data;
|
||||
|
|
|
@ -19,53 +19,48 @@
|
|||
*
|
||||
*************************************************************************/
|
||||
|
||||
/*
|
||||
* Commands common to all known devices.
|
||||
*
|
||||
#define SPI_WRSR 0x01 /* Write status register */
|
||||
#define SPI_WRITE 0x02 /* Write data to memory array */
|
||||
#define SPI_READ 0x03 /* Read data from memory array */
|
||||
#define SPI_WRDI 0x04 /* Reset write enable latch */
|
||||
#define SPI_RDSR 0x05 /* Read status register */
|
||||
#define SPI_WREN 0x06 /* Set write enable latch */
|
||||
|
||||
#define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
|
||||
#define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
|
||||
#define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
|
||||
#define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
|
||||
#define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
|
||||
#define SPI_STATUS_NRDY 0x01 /* Device busy flag */
|
||||
|
||||
/**
|
||||
* struct efx_spi_device - an Efx SPI (Serial Peripheral Interface) device
|
||||
* @efx: The Efx controller that owns this device
|
||||
* @device_id: Controller's id for the device
|
||||
* @size: Size (in bytes)
|
||||
* @addr_len: Number of address bytes in read/write commands
|
||||
* @munge_address: Flag whether addresses should be munged.
|
||||
* Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
|
||||
* use bit 3 of the command byte as address bit A8, rather
|
||||
* than having a two-byte address. If this flag is set, then
|
||||
* commands should be munged in this way.
|
||||
* @block_size: Write block size (in bytes).
|
||||
* Write commands are limited to blocks with this size and alignment.
|
||||
* @read: Read function for the device
|
||||
* @write: Write function for the device
|
||||
*/
|
||||
struct efx_spi_device {
|
||||
struct efx_nic *efx;
|
||||
int device_id;
|
||||
unsigned int size;
|
||||
unsigned int addr_len;
|
||||
unsigned int munge_address:1;
|
||||
unsigned int block_size;
|
||||
};
|
||||
|
||||
/* Write status register */
|
||||
#define SPI_WRSR 0x01
|
||||
|
||||
/* Write data to memory array */
|
||||
#define SPI_WRITE 0x02
|
||||
|
||||
/* Read data from memory array */
|
||||
#define SPI_READ 0x03
|
||||
|
||||
/* Reset write enable latch */
|
||||
#define SPI_WRDI 0x04
|
||||
|
||||
/* Read status register */
|
||||
#define SPI_RDSR 0x05
|
||||
|
||||
/* Set write enable latch */
|
||||
#define SPI_WREN 0x06
|
||||
|
||||
/* SST: Enable write to status register */
|
||||
#define SPI_SST_EWSR 0x50
|
||||
|
||||
/*
|
||||
* Status register bits. Not all bits are supported on all devices.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Write-protect pin enabled */
|
||||
#define SPI_STATUS_WPEN 0x80
|
||||
|
||||
/* Block protection bit 2 */
|
||||
#define SPI_STATUS_BP2 0x10
|
||||
|
||||
/* Block protection bit 1 */
|
||||
#define SPI_STATUS_BP1 0x08
|
||||
|
||||
/* Block protection bit 0 */
|
||||
#define SPI_STATUS_BP0 0x04
|
||||
|
||||
/* State of the write enable latch */
|
||||
#define SPI_STATUS_WEN 0x02
|
||||
|
||||
/* Device busy flag */
|
||||
#define SPI_STATUS_NRDY 0x01
|
||||
int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
|
||||
size_t len, size_t *retlen, u8 *buffer);
|
||||
int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
|
||||
size_t len, size_t *retlen, const u8 *buffer);
|
||||
|
||||
#endif /* EFX_SPI_H */
|
||||
|
|
Reference in a new issue