video: sh7760fb: SH7760/SH7763 LCDC framebuffer driver
Framebuffer driver for the SH7760/SH7763 integrated LCD controller. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Reviewed-by: Paul Mundt <lethal@linux-sh.org> Cc: Krzysztof Helt <krzysztof.h1@poczta.fm> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Siegfried Schaefer <s.schaefer@schaefer-edv.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Nobuhiro Iwamatsu
Linus Torvalds
parent
c6b044d6ba
commit
4a25e41831
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@ -0,0 +1,131 @@
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SH7760/SH7763 integrated LCDC Framebuffer driver
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================================================
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0. Overwiew
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-----------
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The SH7760/SH7763 have an integrated LCD Display controller (LCDC) which
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supports (in theory) resolutions ranging from 1x1 to 1024x1024,
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with color depths ranging from 1 to 16 bits, on STN, DSTN and TFT Panels.
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Caveats:
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* Framebuffer memory must be a large chunk allocated at the top
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of Area3 (HW requirement). Because of this requirement you should NOT
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make the driver a module since at runtime it may become impossible to
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get a large enough contiguous chunk of memory.
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* The driver does not support changing resolution while loaded
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(displays aren't hotpluggable anyway)
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* Heavy flickering may be observed
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a) if you're using 15/16bit color modes at >= 640x480 px resolutions,
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b) during PCMCIA (or any other slow bus) activity.
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* Rotation works only 90degress clockwise, and only if horizontal
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resolution is <= 320 pixels.
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files: drivers/video/sh7760fb.c
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include/asm-sh/sh7760fb.h
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Documentation/fb/sh7760fb.txt
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1. Platform setup
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-----------------
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SH7760:
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Video data is fetched via the DMABRG DMA engine, so you have to
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configure the SH DMAC for DMABRG mode (write 0x94808080 to the
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DMARSRA register somewhere at boot).
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PFC registers PCCR and PCDR must be set to peripheral mode.
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(write zeros to both).
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The driver does NOT do the above for you since board setup is, well, job
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of the board setup code.
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2. Panel definitions
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--------------------
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The LCDC must explicitly be told about the type of LCD panel
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attached. Data must be wrapped in a "struct sh7760fb_platdata" and
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passed to the driver as platform_data.
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Suggest you take a closer look at the SH7760 Manual, Section 30.
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(http://documentation.renesas.com/eng/products/mpumcu/e602291_sh7760.pdf)
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The following code illustrates what needs to be done to
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get the framebuffer working on a 640x480 TFT:
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====================== cut here ======================================
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#include <linux/fb.h>
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#include <asm/sh7760fb.h>
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/*
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* NEC NL6440bc26-01 640x480 TFT
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* dotclock 25175 kHz
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* Xres 640 Yres 480
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* Htotal 800 Vtotal 525
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* HsynStart 656 VsynStart 490
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* HsynLenn 30 VsynLenn 2
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*
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* The linux framebuffer layer does not use the syncstart/synclen
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* values but right/left/upper/lower margin values. The comments
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* for the x_margin explain how to calculate those from given
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* panel sync timings.
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*/
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static struct fb_videomode nl6448bc26 = {
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.name = "NL6448BC26",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39683, /* in picoseconds! */
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.hsync_len = 30,
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.vsync_len = 2,
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.left_margin = 114, /* HTOT - (HSYNSLEN + HSYNSTART) */
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.right_margin = 16, /* HSYNSTART - XRES */
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.upper_margin = 33, /* VTOT - (VSYNLEN + VSYNSTART) */
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.lower_margin = 10, /* VSYNSTART - YRES */
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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};
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static struct sh7760fb_platdata sh7760fb_nl6448 = {
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.def_mode = &nl6448bc26,
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.ldmtr = LDMTR_TFT_COLOR_16, /* 16bit TFT panel */
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.lddfr = LDDFR_8BPP, /* we want 8bit output */
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.ldpmmr = 0x0070,
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.ldpspr = 0x0500,
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.ldaclnr = 0,
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.ldickr = LDICKR_CLKSRC(LCDC_CLKSRC_EXTERNAL) |
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LDICKR_CLKDIV(1),
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.rotate = 0,
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.novsync = 1,
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.blank = NULL,
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};
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/* SH7760:
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* 0xFE300800: 256 * 4byte xRGB palette ram
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* 0xFE300C00: 42 bytes ctrl registers
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*/
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static struct resource sh7760_lcdc_res[] = {
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[0] = {
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.start = 0xFE300800,
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.end = 0xFE300CFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 65,
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.end = 65,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device sh7760_lcdc_dev = {
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.dev = {
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.platform_data = &sh7760fb_nl6448,
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},
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.name = "sh7760-lcdc",
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.id = -1,
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.resource = sh7760_lcdc_res,
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.num_resources = ARRAY_SIZE(sh7760_lcdc_res),
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};
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====================== cut here ======================================
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@ -1991,6 +1991,19 @@ config FB_COBALT
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tristate "Cobalt server LCD frame buffer support"
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depends on FB && MIPS_COBALT
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config FB_SH7760
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bool "SH7760/SH7763 LCDC support"
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depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763)
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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Support for the SH7760/SH7763 integrated (D)STN/TFT LCD Controller.
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Supports display resolutions up to 1024x1024 pixel, grayscale and
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color operation, with depths ranging from 1 bpp to 8 bpp monochrome
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and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
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panels <= 320 pixel horizontal resolution.
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config FB_VIRTUAL
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tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
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depends on FB
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@ -106,6 +106,7 @@ obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
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obj-$(CONFIG_FB_MAXINE) += maxinefb.o
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obj-$(CONFIG_FB_METRONOME) += metronomefb.o
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obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
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obj-$(CONFIG_FB_SH7760) += sh7760fb.o
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obj-$(CONFIG_FB_IMX) += imxfb.o
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obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
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obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
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@ -0,0 +1,658 @@
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/*
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* SH7760/SH7763 LCDC Framebuffer driver.
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*
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* (c) 2006-2008 MSC Vertriebsges.m.b.H.,
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* Manuel Lauss <mano@roarinelk.homelinux.net>
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* (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* PLEASE HAVE A LOOK AT Documentation/fb/sh7760fb.txt!
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*
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* Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
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* for his original source and testing!
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*/
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fb.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <asm/sh7760fb.h>
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struct sh7760fb_par {
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void __iomem *base;
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int irq;
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struct sh7760fb_platdata *pd; /* display information */
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dma_addr_t fbdma; /* physical address */
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int rot; /* rotation enabled? */
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u32 pseudo_palette[16];
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struct platform_device *dev;
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struct resource *ioarea;
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struct completion vsync; /* vsync irq event */
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};
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static irqreturn_t sh7760fb_irq(int irq, void *data)
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{
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struct completion *c = data;
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complete(c);
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return IRQ_HANDLED;
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}
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static void sh7760fb_wait_vsync(struct fb_info *info)
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{
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struct sh7760fb_par *par = info->par;
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if (par->pd->novsync)
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return;
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iowrite16(ioread16(par->base + LDINTR) & ~VINT_CHECK,
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par->base + LDINTR);
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if (par->irq < 0) {
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/* poll for vert. retrace: status bit is sticky */
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while (!(ioread16(par->base + LDINTR) & VINT_CHECK))
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cpu_relax();
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} else {
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/* a "wait_for_irq_event(par->irq)" would be extremely nice */
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init_completion(&par->vsync);
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enable_irq(par->irq);
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wait_for_completion(&par->vsync);
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disable_irq_nosync(par->irq);
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}
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}
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/* wait_for_lps - wait until power supply has reached a certain state. */
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static int wait_for_lps(struct sh7760fb_par *par, int val)
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{
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int i = 100;
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while (--i && ((ioread16(par->base + LDPMMR) & 3) != val))
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msleep(1);
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if (i <= 0)
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return -ETIMEDOUT;
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return 0;
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}
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/* en/disable the LCDC */
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static int sh7760fb_blank(int blank, struct fb_info *info)
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{
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struct sh7760fb_par *par = info->par;
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struct sh7760fb_platdata *pd = par->pd;
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unsigned short cntr = ioread16(par->base + LDCNTR);
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unsigned short intr = ioread16(par->base + LDINTR);
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int lps;
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if (blank == FB_BLANK_UNBLANK) {
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intr |= VINT_START;
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cntr = LDCNTR_DON2 | LDCNTR_DON;
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lps = 3;
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} else {
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intr &= ~VINT_START;
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cntr = LDCNTR_DON2;
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lps = 0;
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}
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if (pd->blank)
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pd->blank(blank);
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iowrite16(intr, par->base + LDINTR);
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iowrite16(cntr, par->base + LDCNTR);
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return wait_for_lps(par, lps);
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}
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/* set color registers */
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static int sh7760fb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
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{
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struct sh7760fb_par *par = info->par;
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u32 s = cmap->start;
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u32 l = cmap->len;
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u16 *r = cmap->red;
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u16 *g = cmap->green;
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u16 *b = cmap->blue;
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u32 col, tmo;
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int ret;
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ret = 0;
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sh7760fb_wait_vsync(info);
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/* request palette access */
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iowrite16(LDPALCR_PALEN, par->base + LDPALCR);
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/* poll for access grant */
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tmo = 100;
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while (!(ioread16(par->base + LDPALCR) & LDPALCR_PALS) && (--tmo))
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cpu_relax();
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if (!tmo) {
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ret = 1;
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dev_dbg(info->dev, "no palette access!\n");
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goto out;
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}
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while (l && (s < 256)) {
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col = ((*r) & 0xff) << 16;
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col |= ((*g) & 0xff) << 8;
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col |= ((*b) & 0xff);
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col &= SH7760FB_PALETTE_MASK;
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if (s < 16)
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((u32 *) (info->pseudo_palette))[s] = s;
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s++;
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l--;
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r++;
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g++;
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b++;
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}
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out:
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iowrite16(0, par->base + LDPALCR);
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return ret;
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}
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static void encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info,
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unsigned long stride)
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{
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memset(fix, 0, sizeof(struct fb_fix_screeninfo));
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strcpy(fix->id, "sh7760-lcdc");
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fix->smem_start = (unsigned long)info->screen_base;
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fix->smem_len = info->screen_size;
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fix->line_length = stride;
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}
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static int sh7760fb_get_color_info(struct device *dev,
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u16 lddfr, int *bpp, int *gray)
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{
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int lbpp, lgray;
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lgray = lbpp = 0;
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switch (lddfr & LDDFR_COLOR_MASK) {
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case LDDFR_1BPP_MONO:
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lgray = 1;
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lbpp = 1;
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break;
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case LDDFR_2BPP_MONO:
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lgray = 1;
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lbpp = 2;
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break;
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case LDDFR_4BPP_MONO:
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lgray = 1;
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case LDDFR_4BPP:
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lbpp = 4;
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break;
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case LDDFR_6BPP_MONO:
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lgray = 1;
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case LDDFR_8BPP:
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lbpp = 8;
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break;
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case LDDFR_16BPP_RGB555:
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case LDDFR_16BPP_RGB565:
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lbpp = 16;
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lgray = 0;
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break;
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default:
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dev_dbg(dev, "unsupported LDDFR bit depth.\n");
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return -EINVAL;
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}
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if (bpp)
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*bpp = lbpp;
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if (gray)
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*gray = lgray;
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return 0;
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}
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static int sh7760fb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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struct fb_fix_screeninfo *fix = &info->fix;
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struct sh7760fb_par *par = info->par;
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int ret, bpp;
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/* get color info from register value */
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ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
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if (ret)
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return ret;
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var->bits_per_pixel = bpp;
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if ((var->grayscale) && (var->bits_per_pixel == 1))
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fix->visual = FB_VISUAL_MONO10;
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else if (var->bits_per_pixel >= 15)
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fix->visual = FB_VISUAL_TRUECOLOR;
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else
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fix->visual = FB_VISUAL_PSEUDOCOLOR;
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/* TODO: add some more validation here */
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return 0;
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}
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/*
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* sh7760fb_set_par - set videomode.
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*
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* NOTE: The rotation, grayscale and DSTN codepaths are
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* totally untested!
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*/
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static int sh7760fb_set_par(struct fb_info *info)
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{
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struct sh7760fb_par *par = info->par;
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struct fb_videomode *vm = par->pd->def_mode;
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unsigned long sbase, dstn_off, ldsarl, stride;
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unsigned short hsynp, hsynw, htcn, hdcn;
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unsigned short vsynp, vsynw, vtln, vdln;
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unsigned short lddfr, ldmtr;
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int ret, bpp, gray;
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par->rot = par->pd->rotate;
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/* rotate only works with xres <= 320 */
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if (par->rot && (vm->xres > 320)) {
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dev_dbg(info->dev, "rotation disabled due to display size\n");
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par->rot = 0;
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}
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/* calculate LCDC reg vals from display parameters */
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hsynp = vm->right_margin + vm->xres;
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hsynw = vm->hsync_len;
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htcn = vm->left_margin + hsynp + hsynw;
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hdcn = vm->xres;
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vsynp = vm->lower_margin + vm->yres;
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vsynw = vm->vsync_len;
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vtln = vm->upper_margin + vsynp + vsynw;
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vdln = vm->yres;
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/* get color info from register value */
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ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, &gray);
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if (ret)
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return ret;
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dev_dbg(info->dev, "%dx%d %dbpp %s (orientation %s)\n", hdcn,
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vdln, bpp, gray ? "grayscale" : "color",
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par->rot ? "rotated" : "normal");
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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lddfr = par->pd->lddfr | (1 << 8);
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#else
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lddfr = par->pd->lddfr & ~(1 << 8);
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||||
#endif
|
||||
|
||||
ldmtr = par->pd->ldmtr;
|
||||
|
||||
if (!(vm->sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
ldmtr |= LDMTR_CL1POL;
|
||||
if (!(vm->sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
ldmtr |= LDMTR_FLMPOL;
|
||||
|
||||
/* shut down LCDC before changing display parameters */
|
||||
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
|
||||
|
||||
iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */
|
||||
iowrite16(ldmtr, par->base + LDMTR); /* polarities */
|
||||
iowrite16(lddfr, par->base + LDDFR); /* color/depth */
|
||||
iowrite16((par->rot ? 1 << 13 : 0), par->base + LDSMR); /* rotate */
|
||||
iowrite16(par->pd->ldpmmr, par->base + LDPMMR); /* Power Management */
|
||||
iowrite16(par->pd->ldpspr, par->base + LDPSPR); /* Power Supply Ctrl */
|
||||
|
||||
/* display resolution */
|
||||
iowrite16(((htcn >> 3) - 1) | (((hdcn >> 3) - 1) << 8),
|
||||
par->base + LDHCNR);
|
||||
iowrite16(vdln - 1, par->base + LDVDLNR);
|
||||
iowrite16(vtln - 1, par->base + LDVTLNR);
|
||||
/* h/v sync signals */
|
||||
iowrite16((vsynp - 1) | ((vsynw - 1) << 12), par->base + LDVSYNR);
|
||||
iowrite16(((hsynp >> 3) - 1) | (((hsynw >> 3) - 1) << 12),
|
||||
par->base + LDHSYNR);
|
||||
/* AC modulation sig */
|
||||
iowrite16(par->pd->ldaclnr, par->base + LDACLNR);
|
||||
|
||||
stride = (par->rot) ? vtln : hdcn;
|
||||
if (!gray)
|
||||
stride *= (bpp + 7) >> 3;
|
||||
else {
|
||||
if (bpp == 1)
|
||||
stride >>= 3;
|
||||
else if (bpp == 2)
|
||||
stride >>= 2;
|
||||
else if (bpp == 4)
|
||||
stride >>= 1;
|
||||
/* 6 bpp == 8 bpp */
|
||||
}
|
||||
|
||||
/* if rotated, stride must be power of 2 */
|
||||
if (par->rot) {
|
||||
unsigned long bit = 1 << 31;
|
||||
while (bit) {
|
||||
if (stride & bit)
|
||||
break;
|
||||
bit >>= 1;
|
||||
}
|
||||
if (stride & ~bit)
|
||||
stride = bit << 1; /* not P-o-2, round up */
|
||||
}
|
||||
iowrite16(stride, par->base + LDLAOR);
|
||||
|
||||
/* set display mem start address */
|
||||
sbase = (unsigned long)par->fbdma;
|
||||
if (par->rot)
|
||||
sbase += (hdcn - 1) * stride;
|
||||
|
||||
iowrite32(sbase, par->base + LDSARU);
|
||||
|
||||
/*
|
||||
* for DSTN need to set address for lower half.
|
||||
* I (mlau) don't know which address to set it to,
|
||||
* so I guessed at (stride * yres/2).
|
||||
*/
|
||||
if (((ldmtr & 0x003f) >= LDMTR_DSTN_MONO_8) &&
|
||||
((ldmtr & 0x003f) <= LDMTR_DSTN_COLOR_16)) {
|
||||
|
||||
dev_dbg(info->dev, " ***** DSTN untested! *****\n");
|
||||
|
||||
dstn_off = stride;
|
||||
if (par->rot)
|
||||
dstn_off *= hdcn >> 1;
|
||||
else
|
||||
dstn_off *= vdln >> 1;
|
||||
|
||||
ldsarl = sbase + dstn_off;
|
||||
} else
|
||||
ldsarl = 0;
|
||||
|
||||
iowrite32(ldsarl, par->base + LDSARL); /* mem for lower half of DSTN */
|
||||
|
||||
encode_fix(&info->fix, info, stride);
|
||||
sh7760fb_check_var(&info->var, info);
|
||||
|
||||
sh7760fb_blank(FB_BLANK_UNBLANK, info); /* panel on! */
|
||||
|
||||
dev_dbg(info->dev, "hdcn : %6d htcn : %6d\n", hdcn, htcn);
|
||||
dev_dbg(info->dev, "hsynw : %6d hsynp : %6d\n", hsynw, hsynp);
|
||||
dev_dbg(info->dev, "vdln : %6d vtln : %6d\n", vdln, vtln);
|
||||
dev_dbg(info->dev, "vsynw : %6d vsynp : %6d\n", vsynw, vsynp);
|
||||
dev_dbg(info->dev, "clksrc: %6d clkdiv: %6d\n",
|
||||
(par->pd->ldickr >> 12) & 3, par->pd->ldickr & 0x1f);
|
||||
dev_dbg(info->dev, "ldpmmr: 0x%04x ldpspr: 0x%04x\n", par->pd->ldpmmr,
|
||||
par->pd->ldpspr);
|
||||
dev_dbg(info->dev, "ldmtr : 0x%04x lddfr : 0x%04x\n", ldmtr, lddfr);
|
||||
dev_dbg(info->dev, "ldlaor: %ld\n", stride);
|
||||
dev_dbg(info->dev, "ldsaru: 0x%08lx ldsarl: 0x%08lx\n", sbase, ldsarl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops sh7760fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_blank = sh7760fb_blank,
|
||||
.fb_check_var = sh7760fb_check_var,
|
||||
.fb_setcmap = sh7760fb_setcmap,
|
||||
.fb_set_par = sh7760fb_set_par,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
};
|
||||
|
||||
static void sh7760fb_free_mem(struct fb_info *info)
|
||||
{
|
||||
struct sh7760fb_par *par = info->par;
|
||||
|
||||
if (!info->screen_base)
|
||||
return;
|
||||
|
||||
dma_free_coherent(info->dev, info->screen_size,
|
||||
info->screen_base, par->fbdma);
|
||||
|
||||
par->fbdma = 0;
|
||||
info->screen_base = NULL;
|
||||
info->screen_size = 0;
|
||||
}
|
||||
|
||||
/* allocate the framebuffer memory. This memory must be in Area3,
|
||||
* (dictated by the DMA engine) and contiguous, at a 512 byte boundary.
|
||||
*/
|
||||
static int sh7760fb_alloc_mem(struct fb_info *info)
|
||||
{
|
||||
struct sh7760fb_par *par = info->par;
|
||||
void *fbmem;
|
||||
unsigned long vram;
|
||||
int ret, bpp;
|
||||
|
||||
if (info->screen_base)
|
||||
return 0;
|
||||
|
||||
/* get color info from register value */
|
||||
ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "colinfo\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* min VRAM: xres_min = 16, yres_min = 1, bpp = 1: 2byte -> 1 page
|
||||
max VRAM: xres_max = 1024, yres_max = 1024, bpp = 16: 2MB */
|
||||
|
||||
vram = info->var.xres * info->var.yres;
|
||||
if (info->var.grayscale) {
|
||||
if (bpp == 1)
|
||||
vram >>= 3;
|
||||
else if (bpp == 2)
|
||||
vram >>= 2;
|
||||
else if (bpp == 4)
|
||||
vram >>= 1;
|
||||
} else if (bpp > 8)
|
||||
vram *= 2;
|
||||
if ((vram < 1) || (vram > 1024 * 2048)) {
|
||||
dev_dbg(info->dev, "too much VRAM required. Check settings\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (vram < PAGE_SIZE)
|
||||
vram = PAGE_SIZE;
|
||||
|
||||
fbmem = dma_alloc_coherent(info->dev, vram, &par->fbdma, GFP_KERNEL);
|
||||
|
||||
if (!fbmem)
|
||||
return -ENOMEM;
|
||||
|
||||
if ((par->fbdma & SH7760FB_DMA_MASK) != SH7760FB_DMA_MASK) {
|
||||
sh7760fb_free_mem(info);
|
||||
dev_err(info->dev, "kernel gave me memory at 0x%08lx, which is"
|
||||
"unusable for the LCDC\n", (unsigned long)par->fbdma);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
info->screen_base = fbmem;
|
||||
info->screen_size = vram;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit sh7760fb_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct fb_info *info;
|
||||
struct resource *res;
|
||||
struct sh7760fb_par *par;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (unlikely(res == NULL)) {
|
||||
dev_err(&pdev->dev, "invalid resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
info = framebuffer_alloc(sizeof(struct sh7760fb_par), &pdev->dev);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
par = info->par;
|
||||
par->dev = pdev;
|
||||
|
||||
par->pd = pdev->dev.platform_data;
|
||||
if (!par->pd) {
|
||||
dev_dbg(info->dev, "no display setup data!\n");
|
||||
ret = -ENODEV;
|
||||
goto out_fb;
|
||||
}
|
||||
|
||||
par->ioarea = request_mem_region(res->start,
|
||||
(res->end - res->start), pdev->name);
|
||||
if (!par->ioarea) {
|
||||
dev_err(&pdev->dev, "mmio area busy\n");
|
||||
ret = -EBUSY;
|
||||
goto out_fb;
|
||||
}
|
||||
|
||||
par->base = ioremap_nocache(res->start, res->end - res->start + 1);
|
||||
if (!par->base) {
|
||||
dev_err(&pdev->dev, "cannot remap\n");
|
||||
ret = -ENODEV;
|
||||
goto out_res;
|
||||
}
|
||||
|
||||
iowrite16(0, par->base + LDINTR); /* disable vsync irq */
|
||||
par->irq = platform_get_irq(pdev, 0);
|
||||
if (par->irq >= 0) {
|
||||
ret = request_irq(par->irq, sh7760fb_irq, 0,
|
||||
"sh7760-lcdc", &par->vsync);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "cannot grab IRQ\n");
|
||||
par->irq = -ENXIO;
|
||||
} else
|
||||
disable_irq_nosync(par->irq);
|
||||
}
|
||||
|
||||
fb_videomode_to_var(&info->var, par->pd->def_mode);
|
||||
|
||||
ret = sh7760fb_alloc_mem(info);
|
||||
if (ret) {
|
||||
dev_dbg(info->dev, "framebuffer memory allocation failed!\n");
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
info->pseudo_palette = par->pseudo_palette;
|
||||
|
||||
/* fixup color register bitpositions. These are fixed by hardware */
|
||||
info->var.red.offset = 11;
|
||||
info->var.red.length = 5;
|
||||
info->var.red.msb_right = 0;
|
||||
|
||||
info->var.green.offset = 5;
|
||||
info->var.green.length = 6;
|
||||
info->var.green.msb_right = 0;
|
||||
|
||||
info->var.blue.offset = 0;
|
||||
info->var.blue.length = 5;
|
||||
info->var.blue.msb_right = 0;
|
||||
|
||||
info->var.transp.offset = 0;
|
||||
info->var.transp.length = 0;
|
||||
info->var.transp.msb_right = 0;
|
||||
|
||||
/* set the DON2 bit now, before cmap allocation, as it will randomize
|
||||
* palette memory.
|
||||
*/
|
||||
iowrite16(LDCNTR_DON2, par->base + LDCNTR);
|
||||
info->fbops = &sh7760fb_ops;
|
||||
|
||||
ret = fb_alloc_cmap(&info->cmap, 256, 0);
|
||||
if (ret) {
|
||||
dev_dbg(info->dev, "Unable to allocate cmap memory\n");
|
||||
goto out_mem;
|
||||
}
|
||||
|
||||
ret = register_framebuffer(info);
|
||||
if (ret < 0) {
|
||||
dev_dbg(info->dev, "cannot register fb!\n");
|
||||
goto out_cmap;
|
||||
}
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
printk(KERN_INFO "%s: memory at phys 0x%08lx-0x%08lx, size %ld KiB\n",
|
||||
pdev->name,
|
||||
(unsigned long)par->fbdma,
|
||||
(unsigned long)(par->fbdma + info->screen_size - 1),
|
||||
info->screen_size >> 10);
|
||||
|
||||
return 0;
|
||||
|
||||
out_cmap:
|
||||
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
|
||||
fb_dealloc_cmap(&info->cmap);
|
||||
out_mem:
|
||||
sh7760fb_free_mem(info);
|
||||
out_unmap:
|
||||
if (par->irq >= 0)
|
||||
free_irq(par->irq, &par->vsync);
|
||||
iounmap(par->base);
|
||||
out_res:
|
||||
release_resource(par->ioarea);
|
||||
kfree(par->ioarea);
|
||||
out_fb:
|
||||
framebuffer_release(info);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit sh7760fb_remove(struct platform_device *dev)
|
||||
{
|
||||
struct fb_info *info = platform_get_drvdata(dev);
|
||||
struct sh7760fb_par *par = info->par;
|
||||
|
||||
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
|
||||
unregister_framebuffer(info);
|
||||
fb_dealloc_cmap(&info->cmap);
|
||||
sh7760fb_free_mem(info);
|
||||
if (par->irq >= 0)
|
||||
free_irq(par->irq, par);
|
||||
iounmap(par->base);
|
||||
release_resource(par->ioarea);
|
||||
kfree(par->ioarea);
|
||||
framebuffer_release(info);
|
||||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sh7760_lcdc_driver = {
|
||||
.driver = {
|
||||
.name = "sh7760-lcdc",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = sh7760fb_probe,
|
||||
.remove = __devexit_p(sh7760fb_remove),
|
||||
};
|
||||
|
||||
static int __init sh7760fb_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh7760_lcdc_driver);
|
||||
}
|
||||
|
||||
static void __exit sh7760fb_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh7760_lcdc_driver);
|
||||
}
|
||||
|
||||
module_init(sh7760fb_init);
|
||||
module_exit(sh7760fb_exit);
|
||||
|
||||
MODULE_AUTHOR("Nobuhiro Iwamatsu, Manuel Lauss");
|
||||
MODULE_DESCRIPTION("FBdev for SH7760/63 integrated LCD Controller");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
|
||||
*
|
||||
* (c) 2006-2008 MSC Vertriebsges.m.b.H.,
|
||||
* Manuel Lauss <mano@roarinelk.homelinux.net>
|
||||
* (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_SH_SH7760FB_H
|
||||
#define _ASM_SH_SH7760FB_H
|
||||
|
||||
/*
|
||||
* some bits of the colormap registers should be written as zero.
|
||||
* create a mask for that.
|
||||
*/
|
||||
#define SH7760FB_PALETTE_MASK 0x00f8fcf8
|
||||
|
||||
/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
|
||||
#define SH7760FB_DMA_MASK 0x0C000000
|
||||
|
||||
/* palette */
|
||||
#define LDPR(x) (((x) << 2))
|
||||
|
||||
/* framebuffer registers and bits */
|
||||
#define LDICKR 0x400
|
||||
#define LDMTR 0x402
|
||||
/* see sh7760fb.h for LDMTR bits */
|
||||
#define LDDFR 0x404
|
||||
#define LDDFR_PABD (1 << 8)
|
||||
#define LDDFR_COLOR_MASK 0x7F
|
||||
#define LDSMR 0x406
|
||||
#define LDSMR_ROT (1 << 13)
|
||||
#define LDSARU 0x408
|
||||
#define LDSARL 0x40c
|
||||
#define LDLAOR 0x410
|
||||
#define LDPALCR 0x412
|
||||
#define LDPALCR_PALS (1 << 4)
|
||||
#define LDPALCR_PALEN (1 << 0)
|
||||
#define LDHCNR 0x414
|
||||
#define LDHSYNR 0x416
|
||||
#define LDVDLNR 0x418
|
||||
#define LDVTLNR 0x41a
|
||||
#define LDVSYNR 0x41c
|
||||
#define LDACLNR 0x41e
|
||||
#define LDINTR 0x420
|
||||
#define LDPMMR 0x424
|
||||
#define LDPSPR 0x426
|
||||
#define LDCNTR 0x428
|
||||
#define LDCNTR_DON (1 << 0)
|
||||
#define LDCNTR_DON2 (1 << 4)
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7763
|
||||
# define LDLIRNR 0x440
|
||||
/* LDINTR bit */
|
||||
# define LDINTR_MINTEN (1 << 15)
|
||||
# define LDINTR_FINTEN (1 << 14)
|
||||
# define LDINTR_VSINTEN (1 << 13)
|
||||
# define LDINTR_VEINTEN (1 << 12)
|
||||
# define LDINTR_MINTS (1 << 11)
|
||||
# define LDINTR_FINTS (1 << 10)
|
||||
# define LDINTR_VSINTS (1 << 9)
|
||||
# define LDINTR_VEINTS (1 << 8)
|
||||
# define VINT_START (LDINTR_VSINTEN)
|
||||
# define VINT_CHECK (LDINTR_VSINTS)
|
||||
#else
|
||||
/* LDINTR bit */
|
||||
# define LDINTR_VINTSEL (1 << 12)
|
||||
# define LDINTR_VINTE (1 << 8)
|
||||
# define LDINTR_VINTS (1 << 0)
|
||||
# define VINT_START (LDINTR_VINTSEL)
|
||||
# define VINT_CHECK (LDINTR_VINTS)
|
||||
#endif
|
||||
|
||||
/* HSYNC polarity inversion */
|
||||
#define LDMTR_FLMPOL (1 << 15)
|
||||
|
||||
/* VSYNC polarity inversion */
|
||||
#define LDMTR_CL1POL (1 << 14)
|
||||
|
||||
/* DISPLAY-ENABLE polarity inversion */
|
||||
#define LDMTR_DISPEN_LOWACT (1 << 13)
|
||||
|
||||
/* DISPLAY DATA BUS polarity inversion */
|
||||
#define LDMTR_DPOL_LOWACT (1 << 12)
|
||||
|
||||
/* AC modulation signal enable */
|
||||
#define LDMTR_MCNT (1 << 10)
|
||||
|
||||
/* Disable output of HSYNC during VSYNC period */
|
||||
#define LDMTR_CL1CNT (1 << 9)
|
||||
|
||||
/* Disable output of VSYNC during VSYNC period */
|
||||
#define LDMTR_CL2CNT (1 << 8)
|
||||
|
||||
/* Display types supported by the LCDC */
|
||||
#define LDMTR_STN_MONO_4 0x00
|
||||
#define LDMTR_STN_MONO_8 0x01
|
||||
#define LDMTR_STN_COLOR_4 0x08
|
||||
#define LDMTR_STN_COLOR_8 0x09
|
||||
#define LDMTR_STN_COLOR_12 0x0A
|
||||
#define LDMTR_STN_COLOR_16 0x0B
|
||||
#define LDMTR_DSTN_MONO_8 0x11
|
||||
#define LDMTR_DSTN_MONO_16 0x13
|
||||
#define LDMTR_DSTN_COLOR_8 0x19
|
||||
#define LDMTR_DSTN_COLOR_12 0x1A
|
||||
#define LDMTR_DSTN_COLOR_16 0x1B
|
||||
#define LDMTR_TFT_COLOR_16 0x2B
|
||||
|
||||
/* framebuffer color layout */
|
||||
#define LDDFR_1BPP_MONO 0x00
|
||||
#define LDDFR_2BPP_MONO 0x01
|
||||
#define LDDFR_4BPP_MONO 0x02
|
||||
#define LDDFR_6BPP_MONO 0x04
|
||||
#define LDDFR_4BPP 0x0A
|
||||
#define LDDFR_8BPP 0x0C
|
||||
#define LDDFR_16BPP_RGB555 0x1D
|
||||
#define LDDFR_16BPP_RGB565 0x2D
|
||||
|
||||
/* LCDC Pixclock sources */
|
||||
#define LCDC_CLKSRC_BUSCLOCK 0
|
||||
#define LCDC_CLKSRC_PERIPHERAL 1
|
||||
#define LCDC_CLKSRC_EXTERNAL 2
|
||||
|
||||
#define LDICKR_CLKSRC(x) \
|
||||
(((x) & 3) << 12)
|
||||
|
||||
/* LCDC pixclock input divider. Set to 1 at a minimum! */
|
||||
#define LDICKR_CLKDIV(x) \
|
||||
((x) & 0x1f)
|
||||
|
||||
struct sh7760fb_platdata {
|
||||
|
||||
/* Set this member to a valid fb_videmode for the display you
|
||||
* wish to use. The following members must be initialized:
|
||||
* xres, yres, hsync_len, vsync_len, sync,
|
||||
* {left,right,upper,lower}_margin.
|
||||
* The driver uses the above members to calculate register values
|
||||
* and memory requirements. Other members are ignored but may
|
||||
* be used by other framebuffer layer components.
|
||||
*/
|
||||
struct fb_videomode *def_mode;
|
||||
|
||||
/* LDMTR includes display type and signal polarity. The
|
||||
* HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
|
||||
* data above; however the polarities of the following signals
|
||||
* must be encoded in the ldmtr member:
|
||||
* Display Enable signal (default high-active) DISPEN_LOWACT
|
||||
* Display Data signals (default high-active) DPOL_LOWACT
|
||||
* AC Modulation signal (default off) MCNT
|
||||
* Hsync-During-Vsync suppression (default off) CL1CNT
|
||||
* Vsync-during-vsync suppression (default off) CL2CNT
|
||||
* NOTE: also set a display type!
|
||||
* (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
|
||||
*/
|
||||
u16 ldmtr;
|
||||
|
||||
/* LDDFR controls framebuffer image format (depth, organization)
|
||||
* Use ONE of the LDDFR_?BPP_* macros!
|
||||
*/
|
||||
u16 lddfr;
|
||||
|
||||
/* LDPMMR and LDPSPR control the timing of the power signals
|
||||
* for the display. Please read the SH7760 Hardware Manual,
|
||||
* Chapters 30.3.17, 30.3.18 and 30.4.6!
|
||||
*/
|
||||
u16 ldpmmr;
|
||||
u16 ldpspr;
|
||||
|
||||
/* LDACLNR contains the line numbers after which the AC modulation
|
||||
* signal is to toggle. Set to ZERO for TFTs or displays which
|
||||
* do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
|
||||
*/
|
||||
u16 ldaclnr;
|
||||
|
||||
/* LDICKR contains information on pixelclock source and config.
|
||||
* Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
|
||||
* minimal value for CLKDIV() must be 1!.
|
||||
*/
|
||||
u16 ldickr;
|
||||
|
||||
/* set this member to 1 if you wish to use the LCDC's hardware
|
||||
* rotation function. This is limited to displays <= 320x200
|
||||
* pixels resolution!
|
||||
*/
|
||||
int rotate; /* set to 1 to rotate 90 CCW */
|
||||
|
||||
/* set this to 1 to suppress vsync irq use. */
|
||||
int novsync;
|
||||
|
||||
/* blanking hook for platform. Set this if your platform can do
|
||||
* more than the LCDC in terms of blanking (e.g. disable clock
|
||||
* generator / backlight power supply / etc.
|
||||
*/
|
||||
void (*blank) (int);
|
||||
};
|
||||
|
||||
#endif /* _ASM_SH_SH7760FB_H */
|
||||
Reference in New Issue