spi: sh-hspi: control spi clock more correctly
Current sh-hspi had used platform-specific speed. This patch remove it, and use spi_transfer specific speed. It removes unnecessary flags from struct sh_hspi_info, but struct sh_hspi_info is still exist, since sh-hspi needs platform info in the future. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Kuninori Morimoto
Grant Likely
parent
ec139b67ad
commit
49e599b859
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@ -22,6 +22,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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@ -50,6 +52,7 @@ struct hspi_priv {
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void __iomem *addr;
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struct spi_master *master;
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struct device *dev;
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struct clk *clk;
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};
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/*
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@ -162,6 +165,59 @@ static int hspi_unprepare_transfer(struct spi_master *master)
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return 0;
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}
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static void hspi_hw_setup(struct hspi_priv *hspi,
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struct spi_message *msg,
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struct spi_transfer *t)
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{
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struct spi_device *spi = msg->spi;
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struct device *dev = hspi->dev;
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u32 target_rate;
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u32 spcr, idiv_clk;
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u32 rate, best_rate, min, tmp;
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target_rate = t ? t->speed_hz : 0;
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if (!target_rate)
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target_rate = spi->max_speed_hz;
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/*
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* find best IDIV/CLKCx settings
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*/
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min = ~0;
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best_rate = 0;
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spcr = 0;
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for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
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rate = clk_get_rate(hspi->clk);
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/* IDIV calculation */
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if (idiv_clk & (1 << 5))
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rate /= 128;
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else
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rate /= 16;
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/* CLKCx calculation */
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rate /= (((idiv_clk & 0x1F) + 1) * 2) ;
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/* save best settings */
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tmp = abs(target_rate - rate);
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if (tmp < min) {
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min = tmp;
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spcr = idiv_clk;
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best_rate = rate;
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}
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}
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if (spi->mode & SPI_CPHA)
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spcr |= 1 << 7;
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if (spi->mode & SPI_CPOL)
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spcr |= 1 << 6;
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dev_dbg(dev, "speed %d/%d\n", target_rate, best_rate);
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hspi_write(hspi, SPCR, spcr);
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hspi_write(hspi, SPSR, 0x0);
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hspi_write(hspi, SPSCR, 0x1); /* master mode */
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}
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static int hspi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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@ -173,6 +229,8 @@ static int hspi_transfer_one_message(struct spi_master *master,
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ret = 0;
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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hspi_hw_setup(hspi, msg, t);
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if (t->tx_buf) {
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ret = hspi_push(hspi, msg, t);
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if (ret < 0)
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@ -197,28 +255,12 @@ static int hspi_setup(struct spi_device *spi)
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{
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struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
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struct device *dev = hspi->dev;
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struct sh_hspi_info *info = hspi2info(hspi);
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u32 data;
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if (8 != spi->bits_per_word) {
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dev_err(dev, "bits_per_word should be 8\n");
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return -EIO;
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}
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/* setup first of all in under pm_runtime */
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data = SH_HSPI_CLK_DIVC(info->flags);
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if (info->flags & SH_HSPI_FBS)
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data |= 1 << 7;
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if (info->flags & SH_HSPI_CLKP_HIGH)
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data |= 1 << 6;
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if (info->flags & SH_HSPI_IDIV_DIV128)
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data |= 1 << 5;
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hspi_write(hspi, SPCR, data);
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hspi_write(hspi, SPSR, 0x0);
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hspi_write(hspi, SPSCR, 0x1); /* master mode */
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dev_dbg(dev, "%s setup\n", spi->modalias);
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return 0;
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@ -237,6 +279,7 @@ static int __devinit hspi_probe(struct platform_device *pdev)
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struct resource *res;
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struct spi_master *master;
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struct hspi_priv *hspi;
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struct clk *clk;
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int ret;
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/* get base addr */
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@ -252,12 +295,20 @@ static int __devinit hspi_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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clk = clk_get(NULL, "shyway_clk");
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if (!clk) {
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dev_err(&pdev->dev, "shyway_clk is required\n");
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ret = -EINVAL;
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goto error0;
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}
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hspi = spi_master_get_devdata(master);
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dev_set_drvdata(&pdev->dev, hspi);
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/* init hspi */
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hspi->master = master;
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hspi->dev = &pdev->dev;
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hspi->clk = clk;
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hspi->addr = devm_ioremap(hspi->dev,
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res->start, resource_size(res));
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if (!hspi->addr) {
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@ -289,6 +340,8 @@ static int __devinit hspi_probe(struct platform_device *pdev)
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error2:
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devm_iounmap(hspi->dev, hspi->addr);
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error1:
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clk_put(clk);
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error0:
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spi_master_put(master);
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return ret;
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@ -300,6 +353,7 @@ static int __devexit hspi_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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clk_put(hspi->clk);
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spi_unregister_master(hspi->master);
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devm_iounmap(hspi->dev, hspi->addr);
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@ -17,18 +17,7 @@
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#ifndef SH_HSPI_H
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#define SH_HSPI_H
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/*
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* flags
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*
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*
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*/
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#define SH_HSPI_CLK_DIVC(d) (d & 0xFF)
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#define SH_HSPI_FBS (1 << 8)
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#define SH_HSPI_CLKP_HIGH (1 << 9) /* default LOW */
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#define SH_HSPI_IDIV_DIV128 (1 << 10) /* default div16 */
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struct sh_hspi_info {
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u32 flags;
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};
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#endif
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