ARM: OMAP2/3: hwmod data: add gpmc
Add gpmc hwmod and associated interconnect data Signed-off-by: Afzal Mohammed <afzal@ti.com> [paul@pwsan.com: added comments to the use of HWMOD_INIT_NO_RESET] Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
230844db90
commit
49484a60ff
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@ -535,6 +535,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
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{ }
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{ }
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};
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};
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static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
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{
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.pa_start = 0x6800a000,
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.pa_end = 0x6800afff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_counter_32k_hwmod,
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.slave = &omap2xxx_counter_32k_hwmod,
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@ -543,6 +552,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2xxx_gpmc_hwmod,
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.clk = "core_l3_ck",
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.addr = omap2420_gpmc_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
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static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
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&omap2xxx_l3_main__l4_core,
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&omap2xxx_l3_main__l4_core,
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&omap2xxx_mpu__l3_main,
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&omap2xxx_mpu__l3_main,
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@ -586,6 +603,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
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&omap2420_l4_core__msdi1,
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&omap2420_l4_core__msdi1,
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&omap2420_l4_core__hdq1w,
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&omap2420_l4_core__hdq1w,
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&omap2420_l4_wkup__counter_32k,
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&omap2420_l4_wkup__counter_32k,
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&omap2420_l3__gpmc,
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NULL,
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NULL,
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};
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};
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@ -887,6 +887,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
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{ }
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{ }
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};
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};
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static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
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{
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.pa_start = 0x6e000000,
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.pa_end = 0x6e000fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_counter_32k_hwmod,
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.slave = &omap2xxx_counter_32k_hwmod,
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@ -895,6 +904,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2xxx_gpmc_hwmod,
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.clk = "core_l3_ck",
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.addr = omap2430_gpmc_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
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static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
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&omap2xxx_l3_main__l4_core,
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&omap2xxx_l3_main__l4_core,
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&omap2xxx_mpu__l3_main,
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&omap2xxx_mpu__l3_main,
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@ -945,6 +962,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
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&omap2430_l4_core__mcbsp5,
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&omap2430_l4_core__mcbsp5,
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&omap2430_l4_core__hdq1w,
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&omap2430_l4_core__hdq1w,
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&omap2430_l4_wkup__counter_32k,
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&omap2430_l4_wkup__counter_32k,
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&omap2430_l3__gpmc,
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NULL,
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NULL,
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};
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};
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@ -172,6 +172,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
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.rev = OMAP2_MCSPI_REV,
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.rev = OMAP2_MCSPI_REV,
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};
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};
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/*
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* 'gpmc' class
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* general purpose memory controller
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*/
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static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
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.name = "gpmc",
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.sysc = &omap2xxx_gpmc_sysc,
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};
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/*
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/*
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* IP blocks
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* IP blocks
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*/
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*/
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@ -724,7 +744,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
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.dev_attr = &omap_mcspi2_dev_attr,
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.dev_attr = &omap_mcspi2_dev_attr,
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};
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};
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static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
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static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
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.name = "counter",
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.name = "counter",
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};
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};
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@ -743,3 +762,33 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
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},
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},
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.class = &omap2xxx_counter_hwmod_class,
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.class = &omap2xxx_counter_hwmod_class,
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};
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};
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/* gpmc */
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static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
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{ .irq = 20 },
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{ .irq = -1 }
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};
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struct omap_hwmod omap2xxx_gpmc_hwmod = {
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.name = "gpmc",
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.class = &omap2xxx_gpmc_hwmod_class,
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.mpu_irqs = omap2xxx_gpmc_irqs,
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.main_clk = "gpmc_fck",
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/*
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* XXX HWMOD_INIT_NO_RESET should not be needed for this IP
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* block. It is not being added due to any known bugs with
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* resetting the GPMC IP block, but rather because any timings
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* set by the bootloader are not being correctly programmed by
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* the kernel from the board file or DT data.
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* HWMOD_INIT_NO_RESET should be removed ASAP.
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*/
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.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
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HWMOD_NO_IDLEST),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 3,
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.module_bit = OMAP24XX_EN_GPMC_MASK,
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.module_offs = CORE_MOD,
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},
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},
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};
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@ -2095,6 +2095,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
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},
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},
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};
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};
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/*
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* 'gpmc' class
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* general purpose memory controller
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*/
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static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
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.name = "gpmc",
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.sysc = &omap3xxx_gpmc_sysc,
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};
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static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
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{ .irq = 20 },
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{ .irq = -1 }
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};
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static struct omap_hwmod omap3xxx_gpmc_hwmod = {
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.name = "gpmc",
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.class = &omap3xxx_gpmc_hwmod_class,
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.clkdm_name = "core_l3_clkdm",
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.mpu_irqs = omap3xxx_gpmc_irqs,
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.main_clk = "gpmc_fck",
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/*
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* XXX HWMOD_INIT_NO_RESET should not be needed for this IP
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* block. It is not being added due to any known bugs with
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* resetting the GPMC IP block, but rather because any timings
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* set by the bootloader are not being correctly programmed by
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* the kernel from the board file or DT data.
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* HWMOD_INIT_NO_RESET should be removed ASAP.
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*/
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.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
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HWMOD_NO_IDLEST),
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};
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/*
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/*
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* interfaces
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* interfaces
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*/
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*/
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@ -3320,6 +3363,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
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{ }
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{ }
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};
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};
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static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
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{
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.pa_start = 0x6e000000,
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.pa_end = 0x6e000fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
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.master = &omap3xxx_l4_wkup_hwmod,
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.master = &omap3xxx_l4_wkup_hwmod,
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.slave = &omap3xxx_counter_32k_hwmod,
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.slave = &omap3xxx_counter_32k_hwmod,
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@ -3429,6 +3481,14 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
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.user = OCP_USER_MPU,
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.user = OCP_USER_MPU,
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};
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};
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_gpmc_hwmod,
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.clk = "core_l3_ick",
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.addr = omap3xxx_gpmc_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_per,
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&omap3xxx_l3_main__l4_per,
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@ -3474,6 +3534,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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&omap34xx_l4_core__mcspi3,
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&omap34xx_l4_core__mcspi3,
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&omap34xx_l4_core__mcspi4,
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&omap34xx_l4_core__mcspi4,
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&omap3xxx_l4_wkup__counter_32k,
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&omap3xxx_l4_wkup__counter_32k,
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&omap3xxx_l3_main__gpmc,
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NULL,
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NULL,
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};
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};
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@ -1352,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
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.name = "gpmc",
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.name = "gpmc",
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.class = &omap44xx_gpmc_hwmod_class,
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.class = &omap44xx_gpmc_hwmod_class,
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.clkdm_name = "l3_2_clkdm",
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.clkdm_name = "l3_2_clkdm",
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/*
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* XXX HWMOD_INIT_NO_RESET should not be needed for this IP
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* block. It is not being added due to any known bugs with
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* resetting the GPMC IP block, but rather because any timings
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* set by the bootloader are not being correctly programmed by
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* the kernel from the board file or DT data.
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* HWMOD_INIT_NO_RESET should be removed ASAP.
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*/
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.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
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.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
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.mpu_irqs = omap44xx_gpmc_irqs,
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.mpu_irqs = omap44xx_gpmc_irqs,
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.sdma_reqs = omap44xx_gpmc_sdma_reqs,
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.sdma_reqs = omap44xx_gpmc_sdma_reqs,
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@ -77,6 +77,7 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
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extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
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extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
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extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
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extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
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extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
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extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
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extern struct omap_hwmod omap2xxx_gpmc_hwmod;
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/* Common interface data across OMAP2xxx */
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/* Common interface data across OMAP2xxx */
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extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
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extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
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@ -109,6 +109,8 @@
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#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
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#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
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#define OMAP2430_EN_USBHS_SHIFT 6
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#define OMAP2430_EN_USBHS_SHIFT 6
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#define OMAP2430_EN_USBHS_MASK (1 << 6)
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#define OMAP2430_EN_USBHS_MASK (1 << 6)
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#define OMAP24XX_EN_GPMC_SHIFT 1
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#define OMAP24XX_EN_GPMC_MASK (1 << 1)
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/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
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/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
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#define OMAP2420_ST_MMC_SHIFT 26
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#define OMAP2420_ST_MMC_SHIFT 26
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