drm/radeon: Drop inlines from evergreen_cs.c / r600_cs.c
Fixes evergreen_cs_parse 4080 23124 +19044 and others compared to a non force inline kernel. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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1c482ab359
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2 changed files with 16 additions and 16 deletions
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@ -122,7 +122,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
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track->db_s_write_bo = NULL;
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}
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static inline int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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{
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/* XXX fill in */
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return 0;
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@ -242,7 +242,7 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
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* Check next packet is relocation packet3, do bo validation and compute
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* GPU offset using the provided start.
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**/
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static inline int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
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static int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
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{
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struct radeon_cs_packet p3reloc;
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int r;
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@ -414,7 +414,7 @@ static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
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* if register is safe. If register is not flag as safe this function
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* will test it against a list of register needind special handling.
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*/
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static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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{
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struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
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struct radeon_cs_reloc *reloc;
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@ -990,7 +990,7 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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* This function will check that the resource has valid field and that
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* the texture and mipmap bo object are big enough to cover this resource.
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*/
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static inline int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
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static int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
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struct radeon_bo *texture,
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struct radeon_bo *mipmap)
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{
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@ -162,7 +162,7 @@ static const struct gpu_formats color_formats_table[] = {
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[V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
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};
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static inline bool fmt_is_valid_color(u32 format)
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static bool fmt_is_valid_color(u32 format)
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{
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if (format >= ARRAY_SIZE(color_formats_table))
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return false;
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@ -173,7 +173,7 @@ static inline bool fmt_is_valid_color(u32 format)
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return false;
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}
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static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family)
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static bool fmt_is_valid_texture(u32 format, enum radeon_family family)
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{
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if (format >= ARRAY_SIZE(color_formats_table))
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return false;
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@ -187,7 +187,7 @@ static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family)
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return false;
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}
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static inline int fmt_get_blocksize(u32 format)
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static int fmt_get_blocksize(u32 format)
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{
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if (format >= ARRAY_SIZE(color_formats_table))
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return 0;
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@ -195,7 +195,7 @@ static inline int fmt_get_blocksize(u32 format)
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return color_formats_table[format].blocksize;
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}
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static inline int fmt_get_nblocksx(u32 format, u32 w)
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static int fmt_get_nblocksx(u32 format, u32 w)
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{
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unsigned bw;
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@ -209,7 +209,7 @@ static inline int fmt_get_nblocksx(u32 format, u32 w)
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return (w + bw - 1) / bw;
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}
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static inline int fmt_get_nblocksy(u32 format, u32 h)
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static int fmt_get_nblocksy(u32 format, u32 h)
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{
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unsigned bh;
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@ -223,7 +223,7 @@ static inline int fmt_get_nblocksy(u32 format, u32 h)
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return (h + bh - 1) / bh;
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}
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static inline int r600_bpe_from_format(u32 *bpe, u32 format)
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static int r600_bpe_from_format(u32 *bpe, u32 format)
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{
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unsigned res;
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@ -252,7 +252,7 @@ struct array_mode_checker {
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};
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/* returns alignment in pixels for pitch/height/depth and bytes for base */
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static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
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static int r600_get_array_mode_alignment(struct array_mode_checker *values,
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u32 *pitch_align,
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u32 *height_align,
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u32 *depth_align,
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@ -331,7 +331,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
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track->db_depth_control = 0xFFFFFFFF;
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}
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static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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{
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struct r600_cs_track *track = p->track;
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u32 slice_tile_max, size, tmp;
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@ -737,7 +737,7 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
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* Check next packet is relocation packet3, do bo validation and compute
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* GPU offset using the provided start.
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**/
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static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
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static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
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{
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struct radeon_cs_packet p3reloc;
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int r;
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@ -911,7 +911,7 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
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* if register is safe. If register is not flag as safe this function
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* will test it against a list of register needind special handling.
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*/
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static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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{
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struct r600_cs_track *track = (struct r600_cs_track *)p->track;
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struct radeon_cs_reloc *reloc;
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@ -1215,7 +1215,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
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return 0;
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}
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static inline unsigned mip_minify(unsigned size, unsigned level)
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static unsigned mip_minify(unsigned size, unsigned level)
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{
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unsigned val;
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@ -1285,7 +1285,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
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* This function will check that the resource has valid field and that
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* the texture and mipmap bo object are big enough to cover this resource.
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*/
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static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
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static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
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struct radeon_bo *texture,
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struct radeon_bo *mipmap,
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u64 base_offset,
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