Staging: pata_rdc: coding style fixes
This fixes a number of coding style issues in the pata_rdc.h file Cc: Kevin Huang <Kevin.Huang@rdc.com.tw> Cc: Tomy Wang <Tomy.Wang@rdc.com.tw> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman
parent
b079fa27d9
commit
482612afc6
File diff suppressed because it is too large
Load Diff
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@ -2,139 +2,136 @@
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#define pata_rdc_H
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#ifndef TRUE
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#define TRUE 1
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#define FALSE 0
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#endif
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// ATA Configuration Register ID offset address size
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#define ATAConfiguration_PCIOffset 0x40
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#define ATAConfiguration_ID_PrimaryTiming 0x00
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#define ATAConfiguration_ID_SecondaryTiming 0x02
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#define ATAConfiguration_ID_Device1Timing 0x04
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#define ATAConfiguration_ID_UDMAControl 0x08
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#define ATAConfiguration_ID_UDMATiming 0x0A
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#define ATAConfiguration_ID_IDEIOConfiguration 0x14
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/* ATA Configuration Register ID offset address size */
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#define ATAConfiguration_PCIOffset 0x40
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#define ATAConfiguration_ID_PrimaryTiming 0x00
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#define ATAConfiguration_ID_SecondaryTiming 0x02
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#define ATAConfiguration_ID_Device1Timing 0x04
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#define ATAConfiguration_ID_UDMAControl 0x08
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#define ATAConfiguration_ID_UDMATiming 0x0A
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#define ATAConfiguration_ID_IDEIOConfiguration 0x14
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#define ATAConfiguration_ID_PrimaryTiming_Size 2
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#define ATAConfiguration_ID_SecondaryTiming_Size 2
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#define ATAConfiguration_ID_Device1Timing_Size 1
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#define ATAConfiguration_ID_UDMAControl_Size 1
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#define ATAConfiguration_ID_UDMATiming_Size 2
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#define ATAConfiguration_ID_IDEIOConfiguration_Size 4
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#define ATAConfiguration_ID_PrimaryTiming_Size 2
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#define ATAConfiguration_ID_SecondaryTiming_Size 2
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#define ATAConfiguration_ID_Device1Timing_Size 1
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#define ATAConfiguration_ID_UDMAControl_Size 1
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#define ATAConfiguration_ID_UDMATiming_Size 2
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#define ATAConfiguration_ID_IDEIOConfiguration_Size 4
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// ATA Configuration Register bit define
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#define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 // PIO 3 or greater
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#define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 // PIO 2 or greater
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#define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008
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#define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010
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#define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 // PIO 3 or greater
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#define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 // PIO 2 or greater
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#define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 // PIO 0, PIO 2, MDMA 0
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 // PIO 3, MDMA 1
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 // X
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 // PIO 4, MDMA 2
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 // PIO 0
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 // PIO 2, MDMA 0
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 // PIO 3, PIO 4, MDMA 1, MDMA 2
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 // X
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#define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000
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#define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000
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/* ATA Configuration Register bit define */
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#define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 /* PIO 3 or greater */
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#define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 /* PIO 2 or greater */
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#define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008
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#define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010
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#define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 /* PIO 3 or greater */
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#define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 /* PIO 2 or greater */
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#define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 /* PIO 0, PIO 2, MDMA 0 */
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 /* PIO 3, MDMA 1 */
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 /* X */
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#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 /* PIO 4, MDMA 2 */
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 /* PIO 0 */
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 /* PIO 2, MDMA 0 */
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 /* PIO 3, PIO 4, MDMA 1, MDMA 2 */
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#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 /* X */
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#define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000
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#define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002
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#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008
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#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020
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#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080
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#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0
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#define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001
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#define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002
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#define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004
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#define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008
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#define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001
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#define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002
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#define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004
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#define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 // UDMA 0
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 // UDMA 1, UDMA 3, UDMA 5
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 // UDMA 2, UDMA 4
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 // X
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 // UDMA 0
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 // UDMA 1, UDMA 3, UDMA 5
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 // UDMA 2, UDMA 4
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 // X
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 // UDMA 0
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 // UDMA 1, UDMA 3, UDMA 5
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 // UDMA 2, UDMA 4
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 // X
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 // UDMA 0
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 // UDMA 1, UDMA 3, UDMA 5
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 // UDMA 2, UDMA 4
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 // X
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 /* UDMA 1, UDMA 3, UDMA 5 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 /* UDMA 2, UDMA 4 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 /* X */
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 /* UDMA 1, UDMA 3, UDMA 5 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 /* UDMA 2, UDMA 4 */
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#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 /* X */
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 /* UDMA 1, UDMA 3, UDMA 5 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 /* UDMA 2, UDMA 4 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 /* X */
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 /* UDMA 1, UDMA 3, UDMA 5 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 /* UDMA 2, UDMA 4 */
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#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 /* X */
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 // UDMA 3, UDMA 4
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008
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#define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 // UDMA 3, UDMA 4, UDMA 5
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 // UDMA 5
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000
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#define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 /* UDMA 3, UDMA 4 */
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008
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#define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 /* UDMA 3, UDMA 4, UDMA 5 */
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 /* UDMA 5 */
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#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000
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#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000
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#define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000
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enum _PIOTimingMode
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{
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PIO0 = 0,
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PIO1,
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PIO2, // MDMA 0
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PIO3, // MDMA 1
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PIO4 // MDMA 2
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enum _PIOTimingMode {
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PIO0 = 0,
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PIO1,
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PIO2, /* MDMA 0 */
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PIO3, /* MDMA 1 */
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PIO4 /* MDMA 2 */
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};
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enum _DMATimingMode
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{
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MDMA0 = 0,
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MDMA1,
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MDMA2
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enum _DMATimingMode {
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MDMA0 = 0,
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MDMA1,
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MDMA2
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};
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enum _UDMATimingMode
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{
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UDMA0 = 0,
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UDMA1,
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UDMA2,
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UDMA3,
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UDMA4,
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UDMA5
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enum _UDMATimingMode {
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UDMA0 = 0,
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UDMA1,
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UDMA2,
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UDMA3,
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UDMA4,
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UDMA5
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};
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@ -144,94 +141,34 @@ enum rdc_controller_ids {
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RDC_17F31012
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};
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// callback function for driver
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/* callback function for driver */
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static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static int __devinit rdc_init_one(
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struct pci_dev *pdev,
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const struct pci_device_id *ent
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);
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/* callback function for ata_port */
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static int rdc_pata_port_start(struct ata_port *ap);
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// callback function for ata_port
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static void rdc_pata_port_stop(struct ata_port *ap);
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static int rdc_pata_port_start(
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struct ata_port *ap
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);
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static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline);
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static void rdc_pata_port_stop(
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struct ata_port *ap
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);
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static int rdc_pata_cable_detect(struct ata_port *ap);
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static int rdc_pata_prereset(
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struct ata_link *link,
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unsigned long deadline
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);
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static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev);
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static int rdc_pata_cable_detect(
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struct ata_port *ap
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);
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static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static void rdc_pata_set_piomode(
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struct ata_port *ap,
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struct ata_device *adev
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);
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/* modified PCIDeviceIO code. */
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static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
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static void rdc_pata_set_dmamode(
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struct ata_port *ap,
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struct ata_device *adev
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);
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static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
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// modified PCIDeviceIO code.
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/* modify ATAHostAdapter code */
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static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
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static uint
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PCIDeviceIO_ReadPCIConfiguration(
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struct pci_dev *pdev,
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uint Offset,
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uint Length,
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void* pBuffer
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);
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static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
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static uint
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PCIDeviceIO_WritePCIConfiguration(
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struct pci_dev *pdev,
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uint Offset,
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uint Length,
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void* pBuffer
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);
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static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
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|
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// modify ATAHostAdapter code
|
||||
|
||||
static uint
|
||||
ATAHostAdapter_SetPrimaryPIO(
|
||||
struct pci_dev *pdev,
|
||||
uint DeviceID,
|
||||
uint PIOTimingMode,
|
||||
uint DMAEnable,
|
||||
uint PrefetchPostingEnable
|
||||
);
|
||||
|
||||
static uint
|
||||
ATAHostAdapter_SetSecondaryPIO(
|
||||
struct pci_dev *pdev,
|
||||
uint DeviceID,
|
||||
uint PIOTimingMode,
|
||||
uint DMAEnable,
|
||||
uint PrefetchPostingEnable
|
||||
);
|
||||
|
||||
static uint
|
||||
ATAHostAdapter_SetPrimaryUDMA(
|
||||
struct pci_dev *pdev,
|
||||
uint DeviceID,
|
||||
uint UDMAEnable,
|
||||
uint UDMATimingMode
|
||||
);
|
||||
|
||||
static uint
|
||||
ATAHostAdapter_SetSecondaryUDMA(
|
||||
struct pci_dev *pdev,
|
||||
uint DeviceID,
|
||||
uint UDMAEnable,
|
||||
uint UDMATimingMode
|
||||
);
|
||||
static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Reference in New Issue