dect: coa: add P640j support
Signed-off-by: Patrick McHardy <kaber@trash.net>
This commit is contained in:
parent
d3f79dd6ed
commit
477bd356e8
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@ -36,3 +36,10 @@ config DECT_COA_FIRMWARE
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is required for this.
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If unsure, say N.
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config DECT_COA_P64
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depends on DECT_COA_PCI && !DECT_COA_CS && DECT_COA_FIRMWARE
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bool "Enable P640 (wideband) support"
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help
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This option enables support for P640j packets, which are used for
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wideband audio. This does not work with the PCMCIA devices.
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@ -15,13 +15,16 @@ clean-files += sc1442x_firmware.h.tmp
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hostprogs-$(CONFIG_DECT_COA_FIRMWARE) += bin2c
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ifeq ($(CONFIG_DECT_COA_FIRMWARE),y)
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ifeq ($(CONFIG_DECT_COA_P64),y)
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ASL_FLAGS = -D ENABLE_P64
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endif
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ASL = asl
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P2BIN = p2bin
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BIN2C = $(obj)/bin2c
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quiet_cmd_asl = ASL $<
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cmd_asl = $(ASL) -q -c $< -o $(<:.asm=.p) -shareout $(<:.asm=.h.tmp); \
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cmd_asl = $(ASL) -q -c $< -o $(<:.asm=.p) $(ASL_FLAGS) -shareout $(<:.asm=.h.tmp); \
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$(P2BIN) $(<:.asm=.p) $(<:.asm=.bin) -r 0-509; \
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$(BIN2C) $(<:.asm=.bin) $(NAME)_firmware > $@; \
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( \
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@ -247,12 +247,16 @@ static const u8 sc1442x_rx_funcs[DECT_PACKET_MAX + 1][DECT_B_MAX + 1][2][2] = {
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[DECT_PACKET_P00][DECT_B_NONE][0][1] = RX_P00_Sync,
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[DECT_PACKET_P32][DECT_B_UNPROTECTED][0][0] = RX_P32U,
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[DECT_PACKET_P32][DECT_B_UNPROTECTED][1][0] = RX_P32U_Enc,
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[DECT_PACKET_P640j][DECT_B_UNPROTECTED][0][0] = RX_P640j,
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[DECT_PACKET_P640j][DECT_B_UNPROTECTED][1][0] = RX_P640j_Enc,
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};
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static const u8 sc1442x_tx_funcs[DECT_PACKET_MAX + 1][DECT_B_MAX + 1][2] = {
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[DECT_PACKET_P00][DECT_B_NONE][0] = TX_P00,
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[DECT_PACKET_P32][DECT_B_UNPROTECTED][0] = TX_P32U,
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[DECT_PACKET_P32][DECT_B_UNPROTECTED][1] = TX_P32U_Enc,
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[DECT_PACKET_P640j][DECT_B_UNPROTECTED][0] = TX_P640j,
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[DECT_PACKET_P640j][DECT_B_UNPROTECTED][1] = TX_P640j_Enc,
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};
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/*
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@ -524,6 +528,8 @@ static void sc1442x_enable(const struct dect_transceiver *trx)
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sc1442x_write_cmd(dev, TX_P32U_Enc, JMP, LoadEncKey);
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sc1442x_write_cmd(dev, RX_P32U_Enc, JMP, LoadEncState);
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sc1442x_write_cmd(dev, TX_P640j_Enc, JMP, LoadEncKey);
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sc1442x_write_cmd(dev, RX_P640j_Enc, JMP, LoadEncState);
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} else {
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sc1442x_write_cmd(dev, ClockSyncOn, P_SC, PSC_S_SYNC_ON);
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sc1442x_write_cmd(dev, ClockAdjust, EN_SL_ADJ, 1);
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@ -531,6 +537,8 @@ static void sc1442x_enable(const struct dect_transceiver *trx)
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sc1442x_write_cmd(dev, RX_P32U_Enc, JMP, LoadEncKey);
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sc1442x_write_cmd(dev, TX_P32U_Enc, JMP, LoadEncState);
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sc1442x_write_cmd(dev, RX_P640j_Enc, JMP, LoadEncKey);
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sc1442x_write_cmd(dev, TX_P640j_Enc, JMP, LoadEncState);
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}
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if (trx->mode == DECT_TRANSCEIVER_MASTER)
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@ -723,7 +731,11 @@ static void sc1442x_tx(const struct dect_transceiver *trx, struct sk_buff *skb)
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const struct dect_transceiver_ops sc1442x_transceiver_ops = {
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.name = "sc1442x",
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.features = DECT_TRANSCEIVER_SLOW_HOPPING,
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.features = DECT_TRANSCEIVER_SLOW_HOPPING |
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#ifdef CONFIG_DECT_COA_P64
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DECT_TRANSCEIVER_PACKET_P64 |
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#endif
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0,
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.eventrate = 6,
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.latency = 6,
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.disable = sc1442x_disable,
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@ -155,6 +155,15 @@ RX_P32U: JMP Receive
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JMP RX_P32U_BZ ; Receive B-field | p: 96 B: 0
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BR WriteBMC2
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RX_P640j_Enc: JMP LoadEncKey
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RX_P640j: JMP Receive
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B_BR SD_B_FIELD_OFF
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JMP Transfer_P640j
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WT 14 ; 15 - 1 (RTN)
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B_XR
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JMP ReceiveEnd
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BR WriteBMC2
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;-------------------------------------------------------------------------------
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; Transmit a P00 packet
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;
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@ -171,6 +180,37 @@ TX_P32U: JMP Transmit ; Transmit S- and beginning of A-field |
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JMP TX_P32U_BZ ; Transmit the B- and Z-fields | p: 96 B: 0
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BR label_54 ;
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TX_P640j_Enc: JMP LoadEncKey
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TX_P640j: JMP Transmit
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B_BT SD_B_FIELD_OFF
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WT 3 ; B_BT has 3 bits of latency
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JMP Transfer_P640j
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WT 11 ; 15 - 1 (RTN) - 3 (latency)
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B_XT
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WT 13 ; 8 (X/Z-Field) + 5
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B_RST
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JMP TransmitEnd
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BR label_58
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Transfer_B: WT 45 ; 47 - 2 (JMP/JMP, JMP/RTN)
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B_XON
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WT 15
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B_XOFF
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RTN
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Transfer_P640j: JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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JMP Transfer_B
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WT 46 ; 47 - 1 (RTN)
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B_XON
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RTN
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;-------------------------------------------------------------------------------
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WriteBMC1: B_WRS SD_BASE_OFF ; write status
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WT 6
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@ -297,10 +337,12 @@ RFInit: RFEN ; Enable RF-clock
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P_LDL 0x20
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WT 10
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IFNDEF ENABLE_P64
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MEN2
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WT 182
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MEN2N
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WT 16
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ENDIF
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RTN
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;--------------------------------------------------------------
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;
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@ -363,7 +405,7 @@ InitDIP: ;B_RST
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WT 10
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P_EN
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P_LD 0x04
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RCK_INT
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;RCK_INT
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RFEN
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RFStart: BR SyncInit
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;-------------------------------------------------------------
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@ -382,8 +424,8 @@ RFStart: BR SyncInit
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SHARED ClockSyncOn,ClockSyncOff,ClockAdjust
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SHARED PSC_ARPD1,PSC_S_SYNC,PSC_S_SYNC_ON,PSC_EOPSM
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SHARED RX_P00,RX_P00_Sync,RX_P32U,RX_P32U_Enc
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SHARED TX_P00,TX_P32U,TX_P32U_Enc
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SHARED RX_P00,RX_P00_Sync,RX_P32U,RX_P32U_Enc,RX_P640j,RX_P640j_Enc
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SHARED TX_P00,TX_P32U,TX_P32U_Enc,TX_P640j,TX_P640j_Enc
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SHARED DCS_IV,DCS_CK,DCS_STATE,DCS_STATE_SIZE
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SHARED LoadEncKey,LoadEncState
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@ -7,7 +7,7 @@
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#include "sc1442x_firmware.h"
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const unsigned char sc1442x_firmware[] = {
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0x01, 0x01, 0x01, 0xd4, 0x0d, 0x00, 0x09, 0x01,
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0x01, 0x01, 0x01, 0xf4, 0x0d, 0x00, 0x09, 0x01,
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0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
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0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
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0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x61, 0x00,
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@ -21,11 +21,20 @@ const unsigned char sc1442x_firmware[] = {
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0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
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0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
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0x09, 0x01, 0x08, 0x01, 0x6f, 0x00, 0x01, 0x02,
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0x02, 0x57, 0x2d, 0x0e, 0x02, 0x83, 0x01, 0x4b,
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0x02, 0x6c, 0x01, 0x39, 0x02, 0xac, 0x02, 0x57,
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0x2d, 0x0e, 0x02, 0x81, 0x01, 0x52, 0x02, 0x86,
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0x02, 0x95, 0x01, 0x4d, 0x02, 0xac, 0x02, 0x86,
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0x25, 0x0e, 0x02, 0x92, 0x01, 0x4e, 0x39, 0x00,
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0x02, 0x7b, 0x2d, 0x0e, 0x02, 0xa7, 0x01, 0x6f,
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0x02, 0x90, 0x01, 0x39, 0x02, 0xcc, 0x02, 0x7b,
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0x2d, 0x0e, 0x02, 0xa5, 0x01, 0x76, 0x02, 0xcc,
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0x02, 0x7b, 0x3c, 0x0e, 0x02, 0x63, 0x09, 0x0e,
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0x2b, 0x00, 0x02, 0xa7, 0x01, 0x76, 0x02, 0xaa,
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0x02, 0xb9, 0x01, 0x71, 0x02, 0xcc, 0x02, 0xaa,
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0x25, 0x0e, 0x02, 0xb6, 0x01, 0x72, 0x02, 0xcc,
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0x02, 0xaa, 0x34, 0x0e, 0x09, 0x03, 0x02, 0x63,
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0x09, 0x0b, 0x24, 0x00, 0x09, 0x0d, 0x20, 0x00,
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0x02, 0xb9, 0x01, 0x78, 0x09, 0x2d, 0x27, 0x00,
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0x09, 0x0f, 0x26, 0x00, 0x04, 0x00, 0x02, 0x5e,
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0x02, 0x5e, 0x02, 0x5e, 0x02, 0x5e, 0x02, 0x5e,
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0x02, 0x5e, 0x02, 0x5e, 0x02, 0x5e, 0x02, 0x5e,
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0x09, 0x2e, 0x27, 0x00, 0x04, 0x00, 0x39, 0x00,
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0x09, 0x06, 0x20, 0x00, 0xec, 0x50, 0x09, 0x05,
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0x08, 0x01, 0x04, 0x00, 0x39, 0x00, 0x09, 0x06,
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0x20, 0x00, 0xec, 0x50, 0x04, 0x00, 0x20, 0x00,
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@ -40,34 +49,25 @@ const unsigned char sc1442x_firmware[] = {
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0x29, 0x00, 0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02,
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0x09, 0x20, 0xea, 0x00, 0x3f, 0x06, 0x09, 0x3d,
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0x04, 0x00, 0x09, 0xf9, 0x09, 0x4f, 0xed, 0x01,
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0xec, 0x40, 0x01, 0xb4, 0xed, 0x00, 0x09, 0x28,
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0xec, 0x40, 0x01, 0xd4, 0xed, 0x00, 0x09, 0x28,
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0x20, 0x00, 0x33, 0x69, 0x08, 0x01, 0x31, 0x00,
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0x09, 0x01, 0xed, 0x10, 0x09, 0x25, 0x37, 0x06,
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0x09, 0x3e, 0x04, 0x00, 0x09, 0xf9, 0x09, 0x54,
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0x20, 0x00, 0xec, 0x10, 0x09, 0x08, 0xec, 0x00,
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0x01, 0xb4, 0x0b, 0x00, 0x09, 0x02, 0xa4, 0x00,
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0x01, 0xd4, 0x0b, 0x00, 0x09, 0x02, 0xa4, 0x00,
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0xb9, 0x65, 0x09, 0x19, 0xa9, 0x00, 0xa5, 0x00,
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0xa4, 0x00, 0xb9, 0x68, 0x09, 0x0a, 0xa9, 0x00,
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0xa5, 0x00, 0xec, 0x20, 0x09, 0x0a, 0xa7, 0x00,
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0x09, 0xb6, 0xa6, 0x00, 0x09, 0x10, 0x04, 0x00,
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0xa5, 0x00, 0xec, 0x20, 0x09, 0x0a, 0x04, 0x00,
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0x40, 0x00, 0x50, 0x70, 0x09, 0x10, 0x50, 0x00,
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0x44, 0x00, 0x09, 0x27, 0x44, 0x00, 0x04, 0x00,
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0x5f, 0x70, 0x09, 0x0b, 0x5f, 0x00, 0x40, 0x00,
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0x04, 0x00, 0x40, 0x00, 0x57, 0x70, 0x09, 0x0b,
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0x57, 0x00, 0x04, 0x00, 0x0f, 0x20, 0x02, 0x99,
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0x57, 0x00, 0x04, 0x00, 0x0f, 0x20, 0x02, 0xbd,
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0x09, 0xfa, 0xea, 0x20, 0xed, 0x42, 0x28, 0x00,
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0x09, 0x40, 0x26, 0x00, 0x29, 0x00, 0x08, 0x14,
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0x03, 0xcd, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
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0x01, 0xbf, 0x08, 0x17, 0xea, 0x00, 0x02, 0x99,
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0x02, 0x38, 0x61, 0x00, 0x08, 0x16, 0x01, 0xbf,
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0x03, 0xed, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
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0x01, 0xdf, 0x08, 0x17, 0xea, 0x00, 0x02, 0xbd,
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0x02, 0x38, 0x61, 0x00, 0x08, 0x16, 0x01, 0xdf,
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0x0f, 0x00, 0xfa, 0x10, 0x09, 0x0a, 0x20, 0x00,
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0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04, 0x62, 0x00,
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0x0b, 0x00, 0x01, 0xbe, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04, 0x0b, 0x00,
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0x01, 0xde, 0xff, 0xff, 0xff, 0xff};
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@ -36,15 +36,15 @@ extern const unsigned char sc1442x_firmware[510];
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#define Slot21 0x30
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#define Slot22 0x32
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#define Slot23 0x34
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#define RFStart 0xDD
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#define RFInit 0x99
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#define SyncInit 0xBE
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#define Sync 0xBF
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#define SyncLock 0xCF
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#define SyncLoop 0xD3
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#define ClockSyncOn 0x60
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#define ClockSyncOff 0x68
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#define ClockAdjust 0x64
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#define RFStart 0xFC
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#define RFInit 0xBD
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#define SyncInit 0xDE
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#define Sync 0xDF
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#define SyncLock 0xEF
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#define SyncLoop 0xF3
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#define ClockSyncOn 0x84
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#define ClockSyncOff 0x8C
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#define ClockAdjust 0x88
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#define PSC_ARPD1 0x80
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#define PSC_S_SYNC 0x40
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#define PSC_S_SYNC_ON 0x20
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@ -53,14 +53,18 @@ extern const unsigned char sc1442x_firmware[510];
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#define RX_P00_Sync 0x3C
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#define RX_P32U 0x3F
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#define RX_P32U_Enc 0x3E
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#define TX_P00 0x43
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#define TX_P32U 0x47
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#define TX_P32U_Enc 0x46
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#define RX_P640j 0x44
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#define RX_P640j_Enc 0x43
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#define TX_P00 0x4B
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#define TX_P32U 0x4F
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#define TX_P32U_Enc 0x4E
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#define TX_P640j 0x54
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#define TX_P640j_Enc 0x53
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#define DCS_IV 0x70
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#define DCS_CK 0x78
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#define DCS_STATE 0x70
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#define DCS_STATE_SIZE 0xB
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#define LoadEncKey 0xAC
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#define LoadEncState 0xB9
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#define LoadEncKey 0xCC
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#define LoadEncState 0xD9
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#endif /* SC1442X_FIRMWARE */
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@ -106,9 +106,11 @@ enum dect_transceiver_stats_attrs {
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/**
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* @DECT_TRANSCEIVER_SLOW_HOPPING: transceiver has slow hopping radio
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* @DECT_TRANSCEIVER_PACKET_P64: transceiver supports packet P640j
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*/
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enum dect_transceiver_features {
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DECT_TRANSCEIVER_SLOW_HOPPING = 0x1,
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DECT_TRANSCEIVER_PACKET_P64 = 0x2,
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};
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enum dect_transceiver_attrs {
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