mfd: Add LPC driver for Intel ICH chipsets
This driver currently creates resources for use by a forthcoming ICH chipset GPIO driver. It could be expanded to create the resources for converting the esb2rom (mtd) and iTCO_wdt (wdt), and potentially more, drivers to use the mfd model. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Aaron Sierra
Samuel Ortiz
parent
f4bf7cf4ca
commit
4630b130b3
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@ -748,6 +748,15 @@ config LPC_SCH
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LPC bridge function of the Intel SCH provides support for
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System Management Bus and General Purpose I/O.
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config LPC_ICH
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tristate "Intel ICH LPC"
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depends on PCI
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select MFD_CORE
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help
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The LPC bridge function of the Intel ICH provides support for
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many functional units. This driver provides needed support for
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other drivers to control these functions, currently GPIO.
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config MFD_RDC321X
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tristate "Support for RDC-R321x southbridge"
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select MFD_CORE
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@ -99,6 +99,7 @@ obj-$(CONFIG_MFD_DB5500_PRCMU) += db5500-prcmu.o
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obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
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obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
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obj-$(CONFIG_LPC_SCH) += lpc_sch.o
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obj-$(CONFIG_LPC_ICH) += lpc_ich.o
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obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o
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obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o
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obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o
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@ -0,0 +1,719 @@
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/*
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* lpc_ich.c - LPC interface for Intel ICH
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*
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* LPC bridge function of the Intel ICH contains many other
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* functional units, such as Interrupt controllers, Timers,
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* Power Management, System Management, GPIO, RTC, and LPC
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* Configuration Registers.
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*
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* This driver is derived from lpc_sch.
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* Copyright (c) 2011 Extreme Engineering Solution, Inc.
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* Author: Aaron Sierra <asierra@xes-inc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* This driver supports the following I/O Controller hubs:
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* (See the intel documentation on http://developer.intel.com.)
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* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
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* document number 290687-002, 298242-027: 82801BA (ICH2)
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* document number 290733-003, 290739-013: 82801CA (ICH3-S)
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* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
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* document number 290744-001, 290745-025: 82801DB (ICH4)
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* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
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* document number 273599-001, 273645-002: 82801E (C-ICH)
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* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
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* document number 300641-004, 300884-013: 6300ESB
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* document number 301473-002, 301474-026: 82801F (ICH6)
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* document number 313082-001, 313075-006: 631xESB, 632xESB
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* document number 307013-003, 307014-024: 82801G (ICH7)
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* document number 322896-001, 322897-001: NM10
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* document number 313056-003, 313057-017: 82801H (ICH8)
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* document number 316972-004, 316973-012: 82801I (ICH9)
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* document number 319973-002, 319974-002: 82801J (ICH10)
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* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
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* document number 320066-003, 320257-008: EP80597 (IICH)
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* document number 324645-001, 324646-001: Cougar Point (CPT)
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* document number TBD : Patsburg (PBG)
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* document number TBD : DH89xxCC
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* document number TBD : Panther Point
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* document number TBD : Lynx Point
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/lpc_ich.h>
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#define ACPIBASE 0x40
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#define ACPIBASE_GPE_OFF 0x28
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#define ACPIBASE_GPE_END 0x2f
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#define ACPICTRL 0x44
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#define GPIOBASE 0x48
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#define GPIOCTRL 0x4C
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static int lpc_ich_acpi_save = -1;
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static int lpc_ich_gpio_save = -1;
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static struct resource gpio_ich_res[] = {
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/* GPIO */
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{
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.flags = IORESOURCE_IO,
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},
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/* ACPI - GPE0 */
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{
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.flags = IORESOURCE_IO,
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},
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};
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enum lpc_cells {
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LPC_GPIO = 0,
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};
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static struct mfd_cell lpc_ich_cells[] = {
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[LPC_GPIO] = {
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.name = "gpio_ich",
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.num_resources = ARRAY_SIZE(gpio_ich_res),
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.resources = gpio_ich_res,
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.ignore_resource_conflicts = true,
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},
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};
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/* chipset related info */
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enum lpc_chipsets {
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LPC_ICH = 0, /* ICH */
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LPC_ICH0, /* ICH0 */
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LPC_ICH2, /* ICH2 */
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LPC_ICH2M, /* ICH2-M */
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LPC_ICH3, /* ICH3-S */
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LPC_ICH3M, /* ICH3-M */
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LPC_ICH4, /* ICH4 */
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LPC_ICH4M, /* ICH4-M */
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LPC_CICH, /* C-ICH */
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LPC_ICH5, /* ICH5 & ICH5R */
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LPC_6300ESB, /* 6300ESB */
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LPC_ICH6, /* ICH6 & ICH6R */
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LPC_ICH6M, /* ICH6-M */
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LPC_ICH6W, /* ICH6W & ICH6RW */
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LPC_631XESB, /* 631xESB/632xESB */
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LPC_ICH7, /* ICH7 & ICH7R */
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LPC_ICH7DH, /* ICH7DH */
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LPC_ICH7M, /* ICH7-M & ICH7-U */
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LPC_ICH7MDH, /* ICH7-M DH */
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LPC_NM10, /* NM10 */
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LPC_ICH8, /* ICH8 & ICH8R */
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LPC_ICH8DH, /* ICH8DH */
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LPC_ICH8DO, /* ICH8DO */
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LPC_ICH8M, /* ICH8M */
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LPC_ICH8ME, /* ICH8M-E */
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LPC_ICH9, /* ICH9 */
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LPC_ICH9R, /* ICH9R */
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LPC_ICH9DH, /* ICH9DH */
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LPC_ICH9DO, /* ICH9DO */
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LPC_ICH9M, /* ICH9M */
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LPC_ICH9ME, /* ICH9M-E */
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LPC_ICH10, /* ICH10 */
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LPC_ICH10R, /* ICH10R */
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LPC_ICH10D, /* ICH10D */
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LPC_ICH10DO, /* ICH10DO */
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LPC_PCH, /* PCH Desktop Full Featured */
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LPC_PCHM, /* PCH Mobile Full Featured */
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LPC_P55, /* P55 */
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LPC_PM55, /* PM55 */
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LPC_H55, /* H55 */
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LPC_QM57, /* QM57 */
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LPC_H57, /* H57 */
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LPC_HM55, /* HM55 */
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LPC_Q57, /* Q57 */
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LPC_HM57, /* HM57 */
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LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
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LPC_QS57, /* QS57 */
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LPC_3400, /* 3400 */
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LPC_3420, /* 3420 */
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LPC_3450, /* 3450 */
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LPC_EP80579, /* EP80579 */
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LPC_CPT, /* Cougar Point */
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LPC_CPTD, /* Cougar Point Desktop */
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LPC_CPTM, /* Cougar Point Mobile */
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LPC_PBG, /* Patsburg */
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LPC_DH89XXCC, /* DH89xxCC */
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LPC_PPT, /* Panther Point */
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LPC_LPT, /* Lynx Point */
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};
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struct lpc_ich_info lpc_chipset_info[] __devinitdata = {
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[LPC_ICH] = {
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.name = "ICH",
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},
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[LPC_ICH0] = {
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.name = "ICH0",
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},
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[LPC_ICH2] = {
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.name = "ICH2",
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},
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[LPC_ICH2M] = {
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.name = "ICH2-M",
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},
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[LPC_ICH3] = {
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.name = "ICH3-S",
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},
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[LPC_ICH3M] = {
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.name = "ICH3-M",
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},
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[LPC_ICH4] = {
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.name = "ICH4",
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},
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[LPC_ICH4M] = {
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.name = "ICH4-M",
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},
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[LPC_CICH] = {
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.name = "C-ICH",
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},
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[LPC_ICH5] = {
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.name = "ICH5 or ICH5R",
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},
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[LPC_6300ESB] = {
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.name = "6300ESB",
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},
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[LPC_ICH6] = {
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.name = "ICH6 or ICH6R",
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.gpio_version = ICH_V6_GPIO,
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},
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[LPC_ICH6M] = {
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.name = "ICH6-M",
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.gpio_version = ICH_V6_GPIO,
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},
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[LPC_ICH6W] = {
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.name = "ICH6W or ICH6RW",
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.gpio_version = ICH_V6_GPIO,
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},
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[LPC_631XESB] = {
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.name = "631xESB/632xESB",
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.gpio_version = ICH_V6_GPIO,
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},
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[LPC_ICH7] = {
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.name = "ICH7 or ICH7R",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH7DH] = {
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.name = "ICH7DH",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH7M] = {
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.name = "ICH7-M or ICH7-U",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH7MDH] = {
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.name = "ICH7-M DH",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_NM10] = {
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.name = "NM10",
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},
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[LPC_ICH8] = {
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.name = "ICH8 or ICH8R",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH8DH] = {
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.name = "ICH8DH",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH8DO] = {
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.name = "ICH8DO",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH8M] = {
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.name = "ICH8M",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH8ME] = {
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.name = "ICH8M-E",
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.gpio_version = ICH_V7_GPIO,
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},
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[LPC_ICH9] = {
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.name = "ICH9",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH9R] = {
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.name = "ICH9R",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH9DH] = {
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.name = "ICH9DH",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH9DO] = {
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.name = "ICH9DO",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH9M] = {
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.name = "ICH9M",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH9ME] = {
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.name = "ICH9M-E",
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.gpio_version = ICH_V9_GPIO,
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},
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[LPC_ICH10] = {
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.name = "ICH10",
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.gpio_version = ICH_V10CONS_GPIO,
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},
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[LPC_ICH10R] = {
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.name = "ICH10R",
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.gpio_version = ICH_V10CONS_GPIO,
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},
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[LPC_ICH10D] = {
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.name = "ICH10D",
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.gpio_version = ICH_V10CORP_GPIO,
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},
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[LPC_ICH10DO] = {
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.name = "ICH10DO",
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.gpio_version = ICH_V10CORP_GPIO,
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},
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[LPC_PCH] = {
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.name = "PCH Desktop Full Featured",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_PCHM] = {
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.name = "PCH Mobile Full Featured",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_P55] = {
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.name = "P55",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_PM55] = {
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.name = "PM55",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_H55] = {
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.name = "H55",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_QM57] = {
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.name = "QM57",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_H57] = {
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.name = "H57",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_HM55] = {
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.name = "HM55",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_Q57] = {
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.name = "Q57",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_HM57] = {
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.name = "HM57",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_PCHMSFF] = {
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.name = "PCH Mobile SFF Full Featured",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_QS57] = {
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.name = "QS57",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_3400] = {
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.name = "3400",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_3420] = {
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.name = "3420",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_3450] = {
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.name = "3450",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_EP80579] = {
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.name = "EP80579",
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},
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[LPC_CPT] = {
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.name = "Cougar Point",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_CPTD] = {
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.name = "Cougar Point Desktop",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_CPTM] = {
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.name = "Cougar Point Mobile",
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.gpio_version = ICH_V5_GPIO,
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},
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[LPC_PBG] = {
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.name = "Patsburg",
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},
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[LPC_DH89XXCC] = {
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.name = "DH89xxCC",
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},
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[LPC_PPT] = {
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.name = "Panther Point",
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},
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[LPC_LPT] = {
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.name = "Lynx Point",
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},
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};
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/*
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* This data only exists for exporting the supported PCI ids
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* via MODULE_DEVICE_TABLE. We do not actually register a
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* pci_driver, because the I/O Controller Hub has also other
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* functions that probably will be registered by other drivers.
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*/
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static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = {
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{ PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
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{ PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
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{ PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
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{ PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
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{ PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
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{ PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
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{ PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
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{ PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
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{ PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
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{ PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
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{ PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
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{ PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
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{ PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
|
||||
{ PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
|
||||
{ PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
|
||||
{ PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
|
||||
{ PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
|
||||
{ PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
|
||||
{ PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
|
||||
{ PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
|
||||
{ PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
|
||||
{ PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
|
||||
{ PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
|
||||
{ PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
|
||||
{ PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
|
||||
{ PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
|
||||
{ PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
|
||||
{ PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
|
||||
{ PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
|
||||
{ PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
|
||||
{ PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
|
||||
{ PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
|
||||
{ PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
|
||||
{ PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
|
||||
{ PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
|
||||
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
|
||||
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
|
||||
{ PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
|
||||
{ PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
|
||||
{ PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
|
||||
{ 0, }, /* End of list */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
|
||||
|
||||
static void lpc_ich_restore_config_space(struct pci_dev *dev)
|
||||
{
|
||||
if (lpc_ich_acpi_save >= 0) {
|
||||
pci_write_config_byte(dev, ACPICTRL, lpc_ich_acpi_save);
|
||||
lpc_ich_acpi_save = -1;
|
||||
}
|
||||
|
||||
if (lpc_ich_gpio_save >= 0) {
|
||||
pci_write_config_byte(dev, GPIOCTRL, lpc_ich_gpio_save);
|
||||
lpc_ich_gpio_save = -1;
|
||||
}
|
||||
}
|
||||
|
||||
static void __devinit lpc_ich_enable_acpi_space(struct pci_dev *dev)
|
||||
{
|
||||
u8 reg_save;
|
||||
|
||||
pci_read_config_byte(dev, ACPICTRL, ®_save);
|
||||
pci_write_config_byte(dev, ACPICTRL, reg_save | 0x10);
|
||||
lpc_ich_acpi_save = reg_save;
|
||||
}
|
||||
|
||||
static void __devinit lpc_ich_enable_gpio_space(struct pci_dev *dev)
|
||||
{
|
||||
u8 reg_save;
|
||||
|
||||
pci_read_config_byte(dev, GPIOCTRL, ®_save);
|
||||
pci_write_config_byte(dev, GPIOCTRL, reg_save | 0x10);
|
||||
lpc_ich_gpio_save = reg_save;
|
||||
}
|
||||
|
||||
static void __devinit lpc_ich_finalize_cell(struct mfd_cell *cell,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
cell->platform_data = &lpc_chipset_info[id->driver_data];
|
||||
cell->pdata_size = sizeof(struct lpc_ich_info);
|
||||
}
|
||||
|
||||
static int __devinit lpc_ich_init_gpio(struct pci_dev *dev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
u32 base_addr_cfg;
|
||||
u32 base_addr;
|
||||
int ret;
|
||||
bool acpi_conflict = false;
|
||||
struct resource *res;
|
||||
|
||||
/* Setup power management base register */
|
||||
pci_read_config_dword(dev, ACPIBASE, &base_addr_cfg);
|
||||
base_addr = base_addr_cfg & 0x0000ff80;
|
||||
if (!base_addr) {
|
||||
dev_err(&dev->dev, "I/O space for ACPI uninitialized\n");
|
||||
lpc_ich_cells[LPC_GPIO].num_resources--;
|
||||
goto gpe0_done;
|
||||
}
|
||||
|
||||
res = &gpio_ich_res[ICH_RES_GPE0];
|
||||
res->start = base_addr + ACPIBASE_GPE_OFF;
|
||||
res->end = base_addr + ACPIBASE_GPE_END;
|
||||
ret = acpi_check_resource_conflict(res);
|
||||
if (ret) {
|
||||
/*
|
||||
* This isn't fatal for the GPIO, but we have to make sure that
|
||||
* the platform_device subsystem doesn't see this resource
|
||||
* or it will register an invalid region.
|
||||
*/
|
||||
lpc_ich_cells[LPC_GPIO].num_resources--;
|
||||
acpi_conflict = true;
|
||||
} else {
|
||||
lpc_ich_enable_acpi_space(dev);
|
||||
}
|
||||
|
||||
gpe0_done:
|
||||
/* Setup GPIO base register */
|
||||
pci_read_config_dword(dev, GPIOBASE, &base_addr_cfg);
|
||||
base_addr = base_addr_cfg & 0x0000ff80;
|
||||
if (!base_addr) {
|
||||
dev_err(&dev->dev, "I/O space for GPIO uninitialized\n");
|
||||
ret = -ENODEV;
|
||||
goto gpio_done;
|
||||
}
|
||||
|
||||
/* Older devices provide fewer GPIO and have a smaller resource size. */
|
||||
res = &gpio_ich_res[ICH_RES_GPIO];
|
||||
res->start = base_addr;
|
||||
switch (lpc_chipset_info[id->driver_data].gpio_version) {
|
||||
case ICH_V5_GPIO:
|
||||
case ICH_V10CORP_GPIO:
|
||||
res->end = res->start + 128 - 1;
|
||||
break;
|
||||
default:
|
||||
res->end = res->start + 64 - 1;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = acpi_check_resource_conflict(res);
|
||||
if (ret) {
|
||||
/* this isn't necessarily fatal for the GPIO */
|
||||
acpi_conflict = true;
|
||||
goto gpio_done;
|
||||
}
|
||||
lpc_ich_enable_gpio_space(dev);
|
||||
|
||||
lpc_ich_finalize_cell(&lpc_ich_cells[LPC_GPIO], id);
|
||||
ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
|
||||
1, NULL, 0);
|
||||
|
||||
gpio_done:
|
||||
if (acpi_conflict)
|
||||
pr_warn("Resource conflict(s) found affecting %s\n",
|
||||
lpc_ich_cells[LPC_GPIO].name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devinit lpc_ich_probe(struct pci_dev *dev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
int ret;
|
||||
bool cell_added = false;
|
||||
|
||||
ret = lpc_ich_init_gpio(dev, id);
|
||||
if (!ret)
|
||||
cell_added = true;
|
||||
|
||||
/*
|
||||
* We only care if at least one or none of the cells registered
|
||||
* successfully.
|
||||
*/
|
||||
if (!cell_added) {
|
||||
lpc_ich_restore_config_space(dev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __devexit lpc_ich_remove(struct pci_dev *dev)
|
||||
{
|
||||
mfd_remove_devices(&dev->dev);
|
||||
lpc_ich_restore_config_space(dev);
|
||||
}
|
||||
|
||||
static struct pci_driver lpc_ich_driver = {
|
||||
.name = "lpc_ich",
|
||||
.id_table = lpc_ich_ids,
|
||||
.probe = lpc_ich_probe,
|
||||
.remove = __devexit_p(lpc_ich_remove),
|
||||
};
|
||||
|
||||
static int __init lpc_ich_init(void)
|
||||
{
|
||||
return pci_register_driver(&lpc_ich_driver);
|
||||
}
|
||||
|
||||
static void __exit lpc_ich_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&lpc_ich_driver);
|
||||
}
|
||||
|
||||
module_init(lpc_ich_init);
|
||||
module_exit(lpc_ich_exit);
|
||||
|
||||
MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
|
||||
MODULE_DESCRIPTION("LPC interface for Intel ICH");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* linux/drivers/mfd/lpc_ich.h
|
||||
*
|
||||
* Copyright (c) 2012 Extreme Engineering Solution, Inc.
|
||||
* Author: Aaron Sierra <asierra@xes-inc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef LPC_ICH_H
|
||||
#define LPC_ICH_H
|
||||
|
||||
/* GPIO resources */
|
||||
#define ICH_RES_GPIO 0
|
||||
#define ICH_RES_GPE0 1
|
||||
|
||||
/* GPIO compatibility */
|
||||
#define ICH_I3100_GPIO 0x401
|
||||
#define ICH_V5_GPIO 0x501
|
||||
#define ICH_V6_GPIO 0x601
|
||||
#define ICH_V7_GPIO 0x701
|
||||
#define ICH_V9_GPIO 0x801
|
||||
#define ICH_V10CORP_GPIO 0xa01
|
||||
#define ICH_V10CONS_GPIO 0xa11
|
||||
|
||||
struct lpc_ich_info {
|
||||
char name[32];
|
||||
unsigned int gpio_version;
|
||||
};
|
||||
|
||||
#endif
|
||||
Reference in New Issue