perf_events, x86: Implement Intel Westmere support
The new Intel documentation includes Westmere arch specific event maps that are significantly different from the Nehalem ones. Add support for this generation. Found the CPUID model numbers on wikipedia. Also ammend some Nehalem constraints, spotted those when looking for the differences between Nehalem and Westmere. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <20100127221122.151865645@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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1 changed files with 117 additions and 7 deletions
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@ -244,18 +244,26 @@ static struct event_constraint intel_core_event_constraints[] =
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static struct event_constraint intel_nehalem_event_constraints[] =
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static struct event_constraint intel_nehalem_event_constraints[] =
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{
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{
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FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
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FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
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FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
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FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
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INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
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INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
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INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
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INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
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INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
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INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
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INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
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INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
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INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
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INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
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INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
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INTEL_EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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INTEL_EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
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EVENT_CONSTRAINT_END
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INTEL_EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
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};
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static struct event_constraint intel_westmere_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
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FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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EVENT_CONSTRAINT_END
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EVENT_CONSTRAINT_END
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};
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};
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@ -286,6 +294,97 @@ static u64 __read_mostly hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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static __initconst u64 westmere_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
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[ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
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[ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
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[ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
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[ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
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[ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static __initconst u64 nehalem_hw_cache_event_ids
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static __initconst u64 nehalem_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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@ -2423,7 +2522,9 @@ static __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_core_event_constraints;
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x86_pmu.event_constraints = intel_core_event_constraints;
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pr_cont("Core2 events, ");
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pr_cont("Core2 events, ");
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break;
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break;
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case 26:
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case 26: /* 45 nm nehalem, "Bloomfield" */
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case 30: /* 45 nm nehalem, "Lynnfield" */
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memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
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memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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sizeof(hw_cache_event_ids));
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@ -2437,6 +2538,15 @@ static __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_gen_event_constraints;
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x86_pmu.event_constraints = intel_gen_event_constraints;
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pr_cont("Atom events, ");
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pr_cont("Atom events, ");
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break;
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break;
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case 37: /* 32 nm nehalem, "Clarkdale" */
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case 44: /* 32 nm nehalem, "Gulftown" */
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memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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x86_pmu.event_constraints = intel_westmere_event_constraints;
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pr_cont("Westmere events, ");
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break;
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default:
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default:
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/*
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/*
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* default constraints for v2 and up
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* default constraints for v2 and up
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