arch/tile: support MMIO-based readb/writeb etc.
Add support for MMIO read/write on tilegx to support GXIO IORPC access. Similar to the asm-generic version, but we include memory fences on the writes to be conservative. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
37b82b5de7
commit
44e5696710
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@ -62,6 +62,92 @@ extern void iounmap(volatile void __iomem *addr);
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#define mm_ptov(addr) ((void *)phys_to_virt(addr))
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#define mm_vtop(addr) ((unsigned long)virt_to_phys(addr))
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#if CHIP_HAS_MMIO()
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/*
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* We use inline assembly to guarantee that the compiler does not
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* split an access into multiple byte-sized accesses as it might
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* sometimes do if a register data structure is marked "packed".
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* Obviously on tile we can't tolerate such an access being
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* actually unaligned, but we want to avoid the case where the
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* compiler conservatively would generate multiple accesses even
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* for an aligned read or write.
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*/
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile u8 __force *)addr;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le16_to_cpu(ret);
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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/* Sign-extend to conform to u32 ABI sign-extension convention. */
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asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le32_to_cpu(ret);
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}
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le64_to_cpu(ret);
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}
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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*(volatile u8 __force *)addr = val;
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}
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
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}
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
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}
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
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}
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/*
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* The on-chip I/O hardware on tilegx is configured with VA=PA for the
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* kernel's PA range. The low-level APIs and field names use "va" and
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* "void *" nomenclature, to be consistent with the general notion
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* that the addresses in question are virtualizable, but in the kernel
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* context we are actually manipulating PA values. (In other contexts,
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* e.g. access from user space, we do in fact use real virtual addresses
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* in the va fields.) To allow readers of the code to understand what's
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* happening, we direct their attention to this comment by using the
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* following two functions that just duplicate __va() and __pa().
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*/
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typedef unsigned long tile_io_addr_t;
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static inline tile_io_addr_t va_to_tile_io_addr(void *va)
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{
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BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
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return __pa(va);
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}
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static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
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{
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return __va(tile_io_addr);
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}
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#else /* CHIP_HAS_MMIO() */
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#ifdef CONFIG_PCI
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extern u8 _tile_readb(unsigned long addr);
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@ -73,10 +159,19 @@ extern void _tile_writew(u16 val, unsigned long addr);
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extern void _tile_writel(u32 val, unsigned long addr);
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extern void _tile_writeq(u64 val, unsigned long addr);
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#else
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#define __raw_readb(addr) _tile_readb((unsigned long)addr)
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#define __raw_readw(addr) _tile_readw((unsigned long)addr)
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#define __raw_readl(addr) _tile_readl((unsigned long)addr)
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#define __raw_readq(addr) _tile_readq((unsigned long)addr)
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#define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
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#define __raw_writew(val, addr) _tile_writew(val, (unsigned long)addr)
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#define __raw_writel(val, addr) _tile_writel(val, (unsigned long)addr)
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#define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
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#else /* CONFIG_PCI */
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/*
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* The Tile architecture does not support IOMEM unless PCI is enabled.
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* The tilepro architecture does not support IOMEM unless PCI is enabled.
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* Unfortunately we can't yet simply not declare these methods,
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* since some generic code that compiles into the kernel, but
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* we never run, uses them unconditionally.
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@ -88,65 +183,58 @@ static inline int iomem_panic(void)
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return 0;
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}
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static inline u8 _tile_readb(unsigned long addr)
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static inline u8 readb(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u16 _tile_readw(unsigned long addr)
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static inline u16 _readw(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u32 _tile_readl(unsigned long addr)
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static inline u32 readl(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u64 _tile_readq(unsigned long addr)
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static inline u64 readq(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline void _tile_writeb(u8 val, unsigned long addr)
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static inline void writeb(u8 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void _tile_writew(u16 val, unsigned long addr)
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static inline void writew(u16 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void _tile_writel(u32 val, unsigned long addr)
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static inline void writel(u32 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void _tile_writeq(u64 val, unsigned long addr)
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static inline void writeq(u64 val, unsigned long addr)
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{
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iomem_panic();
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}
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#endif
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#endif /* CONFIG_PCI */
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#define readb(addr) _tile_readb((unsigned long)addr)
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#define readw(addr) _tile_readw((unsigned long)addr)
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#define readl(addr) _tile_readl((unsigned long)addr)
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#define readq(addr) _tile_readq((unsigned long)addr)
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#define writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
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#define writew(val, addr) _tile_writew(val, (unsigned long)addr)
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#define writel(val, addr) _tile_writel(val, (unsigned long)addr)
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#define writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
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#endif /* CHIP_HAS_MMIO() */
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define __raw_readq readq
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define __raw_writeq writeq
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#define readb __raw_readb
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#define readw __raw_readw
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#define readl __raw_readl
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#define readq __raw_readq
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#define writeb __raw_writeb
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#define writew __raw_writew
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#define writel __raw_writel
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#define writeq __raw_writeq
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#define readb_relaxed readb
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#define readw_relaxed readw
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