[MIPS] Sibyte: Fix interrupt timer off by one bug.
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: The timers need to be loaded with 1 less than the desired interval not the interval itself. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 2 additions and 2 deletions
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@ -75,10 +75,10 @@ void sb1250_time_init(void)
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/* Disable the timer and set up the count */
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/* Disable the timer and set up the count */
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__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
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__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
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#ifdef CONFIG_SIMULATION
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#ifdef CONFIG_SIMULATION
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__raw_writeq(50000 / HZ,
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__raw_writeq((50000 / HZ) - 1,
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IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
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IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
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#else
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#else
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__raw_writeq(1000000 / HZ,
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__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
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IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
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IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
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#endif
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#endif
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