KVM: x86: Virtualize debug registers
So far KVM only had basic x86 debug register support, once introduced to realize guest debugging that way. The guest itself was not able to use those registers. This patch now adds (almost) full support for guest self-debugging via hardware registers. It refactors the code, moving generic parts out of SVM (VMX was already cleaned up by the KVM_SET_GUEST_DEBUG patches), and it ensures that the registers are properly switched between host and guest. This patch also prepares debug register usage by the host. The latter will (once wired-up by the following patch) allow for hardware breakpoints/watchpoints in guest code. If this is enabled, the guest will only see faked debug registers without functionality, but with content reflecting the guest's modifications. Tested on Intel only, but SVM /should/ work as well, but who knows... Known limitations: Trapping on tss switch won't work - most probably on Intel. Credits also go to Joerg Roedel - I used his once posted debugging series as platform for this patch. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Jan Kiszka
Avi Kivity
parent
55934c0bd3
commit
42dbaa5a05
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@ -135,6 +135,19 @@ enum {
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#define KVM_NR_MEM_OBJS 40
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#define KVM_NR_DB_REGS 4
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#define DR6_BD (1 << 13)
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#define DR6_BS (1 << 14)
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#define DR6_FIXED_1 0xffff0ff0
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#define DR6_VOLATILE 0x0000e00f
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#define DR7_BP_EN_MASK 0x000000ff
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#define DR7_GE (1 << 9)
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#define DR7_GD (1 << 13)
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#define DR7_FIXED_1 0x00000400
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#define DR7_VOLATILE 0xffff23ff
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/*
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* We don't want allocation failures within the mmu code, so we preallocate
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* enough memory for a single page fault in a cache.
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@ -334,6 +347,15 @@ struct kvm_vcpu_arch {
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struct mtrr_state_type mtrr_state;
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u32 pat;
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int switch_db_regs;
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unsigned long host_db[KVM_NR_DB_REGS];
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unsigned long host_dr6;
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unsigned long host_dr7;
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unsigned long db[KVM_NR_DB_REGS];
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unsigned long dr6;
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unsigned long dr7;
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unsigned long eff_db[KVM_NR_DB_REGS];
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};
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struct kvm_mem_alias {
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@ -312,7 +312,7 @@ enum vmcs_field {
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#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
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#define TYPE_MOV_TO_DR (0 << 4)
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#define TYPE_MOV_FROM_DR (1 << 4)
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#define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose reg. */
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#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
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/* segment AR */
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@ -18,7 +18,6 @@ static const u32 host_save_user_msrs[] = {
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};
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#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
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#define NUM_DB_REGS 4
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struct kvm_vcpu;
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@ -29,16 +28,11 @@ struct vcpu_svm {
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struct svm_cpu_data *svm_data;
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uint64_t asid_generation;
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unsigned long db_regs[NUM_DB_REGS];
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u64 next_rip;
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u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
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u64 host_gs_base;
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unsigned long host_cr2;
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unsigned long host_db_regs[NUM_DB_REGS];
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unsigned long host_dr6;
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unsigned long host_dr7;
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u32 *msrpm;
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struct vmcb *hsave;
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@ -38,9 +38,6 @@ MODULE_LICENSE("GPL");
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#define IOPM_ALLOC_ORDER 2
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#define MSRPM_ALLOC_ORDER 1
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#define DR7_GD_MASK (1 << 13)
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#define DR6_BD_MASK (1 << 13)
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#define SEG_TYPE_LDT 2
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#define SEG_TYPE_BUSY_TSS16 3
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@ -181,32 +178,6 @@ static inline void kvm_write_cr2(unsigned long val)
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asm volatile ("mov %0, %%cr2" :: "r" (val));
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}
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static inline unsigned long read_dr6(void)
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{
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unsigned long dr6;
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asm volatile ("mov %%dr6, %0" : "=r" (dr6));
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return dr6;
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}
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static inline void write_dr6(unsigned long val)
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{
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asm volatile ("mov %0, %%dr6" :: "r" (val));
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}
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static inline unsigned long read_dr7(void)
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{
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unsigned long dr7;
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asm volatile ("mov %%dr7, %0" : "=r" (dr7));
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return dr7;
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}
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static inline void write_dr7(unsigned long val)
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{
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asm volatile ("mov %0, %%dr7" :: "r" (val));
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}
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static inline void force_new_asid(struct kvm_vcpu *vcpu)
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{
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to_svm(vcpu)->asid_generation--;
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@ -695,7 +666,6 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
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clear_page(svm->vmcb);
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svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
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svm->asid_generation = 0;
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memset(svm->db_regs, 0, sizeof(svm->db_regs));
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init_vmcb(svm);
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fx_init(&svm->vcpu);
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@ -1035,7 +1005,29 @@ static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
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static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
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{
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unsigned long val = to_svm(vcpu)->db_regs[dr];
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struct vcpu_svm *svm = to_svm(vcpu);
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unsigned long val;
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switch (dr) {
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case 0 ... 3:
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val = vcpu->arch.db[dr];
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break;
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case 6:
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
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val = vcpu->arch.dr6;
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else
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val = svm->vmcb->save.dr6;
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break;
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case 7:
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
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val = vcpu->arch.dr7;
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else
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val = svm->vmcb->save.dr7;
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break;
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default:
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val = 0;
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}
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KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
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return val;
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}
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@ -1045,33 +1037,40 @@ static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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*exception = 0;
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KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
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if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
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svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
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svm->vmcb->save.dr6 |= DR6_BD_MASK;
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*exception = DB_VECTOR;
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return;
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}
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*exception = 0;
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switch (dr) {
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case 0 ... 3:
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svm->db_regs[dr] = value;
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vcpu->arch.db[dr] = value;
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if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
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vcpu->arch.eff_db[dr] = value;
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return;
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case 4 ... 5:
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if (vcpu->arch.cr4 & X86_CR4_DE) {
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if (vcpu->arch.cr4 & X86_CR4_DE)
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*exception = UD_VECTOR;
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return;
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}
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case 7: {
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if (value & ~((1ULL << 32) - 1)) {
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return;
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case 6:
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if (value & 0xffffffff00000000ULL) {
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*exception = GP_VECTOR;
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return;
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}
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svm->vmcb->save.dr7 = value;
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vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
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return;
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case 7:
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if (value & 0xffffffff00000000ULL) {
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*exception = GP_VECTOR;
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return;
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}
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vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
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if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
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svm->vmcb->save.dr7 = vcpu->arch.dr7;
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vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
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}
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return;
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}
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default:
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/* FIXME: Possible case? */
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printk(KERN_DEBUG "%s: unexpected dr %u\n",
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__func__, dr);
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*exception = UD_VECTOR;
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@ -2365,22 +2364,6 @@ static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
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return 0;
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}
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static void save_db_regs(unsigned long *db_regs)
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{
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asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
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asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
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asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
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asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
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}
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static void load_db_regs(unsigned long *db_regs)
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{
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asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
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asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
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asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
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asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
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}
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static void svm_flush_tlb(struct kvm_vcpu *vcpu)
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{
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force_new_asid(vcpu);
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@ -2439,20 +2422,12 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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gs_selector = kvm_read_gs();
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ldt_selector = kvm_read_ldt();
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svm->host_cr2 = kvm_read_cr2();
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svm->host_dr6 = read_dr6();
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svm->host_dr7 = read_dr7();
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if (!is_nested(svm))
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svm->vmcb->save.cr2 = vcpu->arch.cr2;
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/* required for live migration with NPT */
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if (npt_enabled)
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svm->vmcb->save.cr3 = vcpu->arch.cr3;
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if (svm->vmcb->save.dr7 & 0xff) {
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write_dr7(0);
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save_db_regs(svm->host_db_regs);
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load_db_regs(svm->db_regs);
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}
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clgi();
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local_irq_enable();
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@ -2528,16 +2503,11 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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#endif
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);
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if ((svm->vmcb->save.dr7 & 0xff))
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load_db_regs(svm->host_db_regs);
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vcpu->arch.cr2 = svm->vmcb->save.cr2;
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vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
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vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
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vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
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write_dr6(svm->host_dr6);
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write_dr7(svm->host_dr7);
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kvm_write_cr2(svm->host_cr2);
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kvm_load_fs(fs_selector);
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@ -2311,7 +2311,6 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
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kvm_rip_write(vcpu, 0);
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kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
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/* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
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vmcs_writel(GUEST_DR7, 0x400);
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vmcs_writel(GUEST_GDTR_BASE, 0);
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@ -2577,7 +2576,7 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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u32 intr_info, ex_no, error_code;
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unsigned long cr2, rip;
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unsigned long cr2, rip, dr6;
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u32 vect_info;
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enum emulation_result er;
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@ -2637,14 +2636,28 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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}
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ex_no = intr_info & INTR_INFO_VECTOR_MASK;
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if (ex_no == DB_VECTOR || ex_no == BP_VECTOR) {
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switch (ex_no) {
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case DB_VECTOR:
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dr6 = vmcs_readl(EXIT_QUALIFICATION);
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if (!(vcpu->guest_debug &
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(KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
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vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
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kvm_queue_exception(vcpu, DB_VECTOR);
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return 1;
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}
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kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
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kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
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/* fall through */
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case BP_VECTOR:
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kvm_run->exit_reason = KVM_EXIT_DEBUG;
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kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
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kvm_run->debug.arch.exception = ex_no;
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} else {
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break;
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default:
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kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
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kvm_run->ex.exception = ex_no;
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kvm_run->ex.error_code = error_code;
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break;
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}
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return 0;
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}
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@ -2784,21 +2797,44 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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unsigned long val;
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int dr, reg;
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/*
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* FIXME: this code assumes the host is debugging the guest.
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* need to deal with guest debugging itself too.
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*/
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dr = vmcs_readl(GUEST_DR7);
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if (dr & DR7_GD) {
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/*
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* As the vm-exit takes precedence over the debug trap, we
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* need to emulate the latter, either for the host or the
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* guest debugging itself.
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*/
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
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kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
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kvm_run->debug.arch.dr7 = dr;
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kvm_run->debug.arch.pc =
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vmcs_readl(GUEST_CS_BASE) +
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vmcs_readl(GUEST_RIP);
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kvm_run->debug.arch.exception = DB_VECTOR;
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kvm_run->exit_reason = KVM_EXIT_DEBUG;
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return 0;
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} else {
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vcpu->arch.dr7 &= ~DR7_GD;
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vcpu->arch.dr6 |= DR6_BD;
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vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
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kvm_queue_exception(vcpu, DB_VECTOR);
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return 1;
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}
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}
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exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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dr = exit_qualification & 7;
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reg = (exit_qualification >> 8) & 15;
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if (exit_qualification & 16) {
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/* mov from dr */
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dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
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reg = DEBUG_REG_ACCESS_REG(exit_qualification);
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if (exit_qualification & TYPE_MOV_FROM_DR) {
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switch (dr) {
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case 0 ... 3:
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val = vcpu->arch.db[dr];
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break;
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case 6:
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val = 0xffff0ff0;
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val = vcpu->arch.dr6;
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break;
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case 7:
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val = 0x400;
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val = vcpu->arch.dr7;
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break;
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default:
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val = 0;
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@ -2806,7 +2842,38 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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kvm_register_write(vcpu, reg, val);
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KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
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} else {
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/* mov to dr */
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val = vcpu->arch.regs[reg];
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switch (dr) {
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case 0 ... 3:
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vcpu->arch.db[dr] = val;
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if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
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vcpu->arch.eff_db[dr] = val;
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break;
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case 4 ... 5:
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if (vcpu->arch.cr4 & X86_CR4_DE)
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kvm_queue_exception(vcpu, UD_VECTOR);
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break;
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case 6:
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if (val & 0xffffffff00000000ULL) {
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kvm_queue_exception(vcpu, GP_VECTOR);
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break;
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}
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vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
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break;
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case 7:
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if (val & 0xffffffff00000000ULL) {
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kvm_queue_exception(vcpu, GP_VECTOR);
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break;
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}
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vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
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if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
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vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
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vcpu->arch.switch_db_regs =
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(val & DR7_BP_EN_MASK);
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}
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break;
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}
|
||||
KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
|
||||
}
|
||||
skip_emulated_instruction(vcpu);
|
||||
return 1;
|
||||
|
|
@ -2957,7 +3024,18 @@ static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
|||
}
|
||||
tss_selector = exit_qualification;
|
||||
|
||||
return kvm_task_switch(vcpu, tss_selector, reason);
|
||||
if (!kvm_task_switch(vcpu, tss_selector, reason))
|
||||
return 0;
|
||||
|
||||
/* clear all local breakpoint enable flags */
|
||||
vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
|
||||
|
||||
/*
|
||||
* TODO: What about debug traps on tss switch?
|
||||
* Are we supposed to inject them and update dr6?
|
||||
*/
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
||||
|
|
@ -3342,6 +3420,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
|||
*/
|
||||
vmcs_writel(HOST_CR0, read_cr0());
|
||||
|
||||
set_debugreg(vcpu->arch.dr6, 6);
|
||||
|
||||
asm(
|
||||
/* Store host registers */
|
||||
"push %%"R"dx; push %%"R"bp;"
|
||||
|
|
@ -3436,6 +3516,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
|||
vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
|
||||
vcpu->arch.regs_dirty = 0;
|
||||
|
||||
get_debugreg(vcpu->arch.dr6, 6);
|
||||
|
||||
vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
|
||||
if (vmx->rmode.irq.pending)
|
||||
fixup_rmode_irq(vmx);
|
||||
|
|
|
|||
|
|
@ -3025,10 +3025,34 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
|||
|
||||
kvm_guest_enter();
|
||||
|
||||
get_debugreg(vcpu->arch.host_dr6, 6);
|
||||
get_debugreg(vcpu->arch.host_dr7, 7);
|
||||
if (unlikely(vcpu->arch.switch_db_regs)) {
|
||||
get_debugreg(vcpu->arch.host_db[0], 0);
|
||||
get_debugreg(vcpu->arch.host_db[1], 1);
|
||||
get_debugreg(vcpu->arch.host_db[2], 2);
|
||||
get_debugreg(vcpu->arch.host_db[3], 3);
|
||||
|
||||
set_debugreg(0, 7);
|
||||
set_debugreg(vcpu->arch.eff_db[0], 0);
|
||||
set_debugreg(vcpu->arch.eff_db[1], 1);
|
||||
set_debugreg(vcpu->arch.eff_db[2], 2);
|
||||
set_debugreg(vcpu->arch.eff_db[3], 3);
|
||||
}
|
||||
|
||||
KVMTRACE_0D(VMENTRY, vcpu, entryexit);
|
||||
kvm_x86_ops->run(vcpu, kvm_run);
|
||||
|
||||
if (unlikely(vcpu->arch.switch_db_regs)) {
|
||||
set_debugreg(0, 7);
|
||||
set_debugreg(vcpu->arch.host_db[0], 0);
|
||||
set_debugreg(vcpu->arch.host_db[1], 1);
|
||||
set_debugreg(vcpu->arch.host_db[2], 2);
|
||||
set_debugreg(vcpu->arch.host_db[3], 3);
|
||||
}
|
||||
set_debugreg(vcpu->arch.host_dr6, 6);
|
||||
set_debugreg(vcpu->arch.host_dr7, 7);
|
||||
|
||||
vcpu->guest_mode = 0;
|
||||
local_irq_enable();
|
||||
|
||||
|
|
@ -4035,6 +4059,11 @@ int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
|
|||
vcpu->arch.nmi_pending = false;
|
||||
vcpu->arch.nmi_injected = false;
|
||||
|
||||
vcpu->arch.switch_db_regs = 0;
|
||||
memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
|
||||
vcpu->arch.dr6 = DR6_FIXED_1;
|
||||
vcpu->arch.dr7 = DR7_FIXED_1;
|
||||
|
||||
return kvm_x86_ops->vcpu_reset(vcpu);
|
||||
}
|
||||
|
||||
|
|
|
|||
Reference in New Issue