ath9k_hw: AR9003 does not have AR_RC_AHB skip its setting
AR9003 does not have a reset control for AHB. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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1 changed files with 19 additions and 5 deletions
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@ -1697,11 +1697,16 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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if (tmpReg &
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(AR_INTR_SYNC_LOCAL_TIMEOUT |
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AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
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u32 val;
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
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REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
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} else {
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val = AR_RC_HOSTIF;
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if (!AR_SREV_9300_20_OR_LATER(ah))
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val |= AR_RC_AHB;
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REG_WRITE(ah, AR_RC, val);
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} else if (!AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_RC, AR_RC_AHB);
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}
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rst_flags = AR_RTC_RC_MAC_WARM;
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if (type == ATH9K_RESET_COLD)
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@ -1732,7 +1737,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
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REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
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AR_RTC_FORCE_WAKE_ON_INT);
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if (!AR_SREV_9100(ah))
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if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_RC, AR_RC_AHB);
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REG_WRITE(ah, AR_RTC_RESET, 0);
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@ -2413,15 +2418,24 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
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/* Power Management (Chipset) */
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/******************************/
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/*
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* Notify Power Mgt is disabled in self-generated frames.
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* If requested, force chip to sleep.
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*/
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static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
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{
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REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
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if (setChip) {
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/*
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* Clear the RTC force wake bit to allow the
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* mac to go to sleep.
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*/
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REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
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AR_RTC_FORCE_WAKE_EN);
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if (!AR_SREV_9100(ah))
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if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
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/* Shutdown chip. Active low */
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if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
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REG_CLR_BIT(ah, (AR_RTC_RESET),
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AR_RTC_RESET_EN);
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