amd64_edac: Improve DRAM address mapping
Drop static tables which map the bits in F2x80 to a chip select size in favor of functions doing the mapping with some bit fiddling. Also, add F15 support. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
5a5d237169
commit
41d8bfaba7
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@ -24,51 +24,6 @@ static atomic_t drv_instances = ATOMIC_INIT(0);
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static struct mem_ctl_info **mcis;
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static struct ecc_settings **ecc_stngs;
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/*
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* Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and
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* later.
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*/
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static int ddr2_dbam_revCG[] = {
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[0] = 32,
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[1] = 64,
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[2] = 128,
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[3] = 256,
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[4] = 512,
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[5] = 1024,
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[6] = 2048,
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};
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static int ddr2_dbam_revD[] = {
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[0] = 32,
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[1] = 64,
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[2 ... 3] = 128,
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[4] = 256,
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[5] = 512,
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[6] = 256,
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[7] = 512,
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[8 ... 9] = 1024,
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[10] = 2048,
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};
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static int ddr2_dbam[] = { [0] = 128,
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[1] = 256,
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[2 ... 4] = 512,
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[5 ... 6] = 1024,
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[7 ... 8] = 2048,
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[9 ... 10] = 4096,
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[11] = 8192,
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};
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static int ddr3_dbam[] = { [0] = -1,
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[1] = 256,
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[2] = 512,
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[3 ... 4] = -1,
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[5 ... 6] = 1024,
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[7 ... 8] = 2048,
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[9 ... 10] = 4096,
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[11] = 8192,
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};
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/*
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* Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
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* bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
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@ -76,8 +31,6 @@ static int ddr3_dbam[] = { [0] = -1,
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*
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*FIXME: Produce a better mapping/linearisation.
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*/
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struct scrubrate {
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u32 scrubval; /* bit pattern for scrub rate */
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u32 bandwidth; /* bandwidth consumed (bytes/sec) */
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@ -962,7 +915,7 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
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if (pvt->ext_model >= K8_REV_F)
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/* RevF (NPT) and later */
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flag = pvt->dclr0 & F10_WIDTH_128;
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flag = pvt->dclr0 & WIDTH_128;
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else
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/* RevE and earlier */
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flag = pvt->dclr0 & REVE_WIDTH_128;
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@ -1062,18 +1015,41 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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}
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}
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static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
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static int ddr2_cs_size(unsigned i, bool dct_width)
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{
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int *dbam_map;
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unsigned shift = 0;
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if (pvt->ext_model >= K8_REV_F)
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dbam_map = ddr2_dbam;
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else if (pvt->ext_model >= K8_REV_D)
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dbam_map = ddr2_dbam_revD;
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if (i <= 2)
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shift = i;
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else if (!(i & 0x1))
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shift = i >> 1;
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else
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dbam_map = ddr2_dbam_revCG;
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shift = (i + 1) >> 1;
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return dbam_map[cs_mode];
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return 128 << (shift + !!dct_width);
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}
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static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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unsigned cs_mode)
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{
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u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
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if (pvt->ext_model >= K8_REV_F) {
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WARN_ON(cs_mode > 11);
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return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
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}
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else if (pvt->ext_model >= K8_REV_D) {
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WARN_ON(cs_mode > 10);
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if (cs_mode == 3 || cs_mode == 8)
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return 32 << (cs_mode - 1);
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else
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return 32 << cs_mode;
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}
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else {
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WARN_ON(cs_mode > 6);
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return 32 << cs_mode;
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}
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}
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/*
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@ -1089,7 +1065,7 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt)
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int i, j, channels = 0;
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/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
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if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & F10_WIDTH_128))
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if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128))
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return 2;
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/*
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@ -1126,16 +1102,50 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt)
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return channels;
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}
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static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
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static int ddr3_cs_size(unsigned i, bool dct_width)
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{
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int *dbam_map;
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unsigned shift = 0;
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int cs_size = 0;
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if (i == 0 || i == 3 || i == 4)
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cs_size = -1;
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else if (i <= 2)
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shift = i;
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else if (i == 12)
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shift = 7;
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else if (!(i & 0x1))
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shift = i >> 1;
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else
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shift = (i + 1) >> 1;
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if (cs_size != -1)
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cs_size = (128 * (1 << !!dct_width)) << shift;
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return cs_size;
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}
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static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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unsigned cs_mode)
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{
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u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
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WARN_ON(cs_mode > 11);
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if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
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dbam_map = ddr3_dbam;
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return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
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else
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dbam_map = ddr2_dbam;
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return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
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}
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return dbam_map[cs_mode];
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/*
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* F15h supports only 64bit DCT interfaces
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*/
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static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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unsigned cs_mode)
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{
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WARN_ON(cs_mode > 12);
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return ddr3_cs_size(cs_mode, false);
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}
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static void read_dram_ctl_register(struct amd64_pvt *pvt)
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@ -1528,7 +1538,7 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
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u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
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if (boot_cpu_data.x86 == 0xf) {
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if (pvt->dclr0 & F10_WIDTH_128)
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if (pvt->dclr0 & WIDTH_128)
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factor = 1;
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/* K8 families < revF not supported yet */
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@ -1551,11 +1561,13 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
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size0 = 0;
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if (dcsb[dimm*2] & DCSB_CS_ENABLE)
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size0 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
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size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
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DBAM_DIMM(dimm, dbam));
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size1 = 0;
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if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
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size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
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size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
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DBAM_DIMM(dimm, dbam));
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amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
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dimm * 2, size0 << factor,
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@ -1591,6 +1603,7 @@ static struct amd64_family_type amd64_family_types[] = {
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f15_dbam_to_chip_select,
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.read_dct_pci_cfg = f15_read_dct_pci_cfg,
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}
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},
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@ -2030,7 +2043,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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* encompasses
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*
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*/
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static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
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static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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{
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u32 cs_mode, nr_pages;
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@ -2043,7 +2056,7 @@ static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
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*/
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cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
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nr_pages = pvt->ops->dbam_to_cs(pvt, cs_mode) << (20 - PAGE_SHIFT);
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nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
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/*
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* If dual channel then double the memory size of single channel.
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@ -2091,7 +2104,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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i, pvt->mc_node_id);
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empty = 0;
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csrow->nr_pages = amd64_csrow_nr_pages(i, pvt);
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csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
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sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
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csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
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@ -221,7 +221,7 @@
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#define DCLR0 0x90
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#define DCLR1 0x190
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#define REVE_WIDTH_128 BIT(16)
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#define F10_WIDTH_128 BIT(11)
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#define WIDTH_128 BIT(11)
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#define DCHR0 0x94
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#define DCHR1 0x194
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@ -445,7 +445,7 @@ struct low_ops {
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int (*early_channel_count) (struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
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u16 syndrome);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
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int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
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u32 *val, const char *func);
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};
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