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pinctrl: samsung: Assing pin numbers dynamically 

This patch modifies the pinctrl-samsung driver to assign numbers to pins
dynamically instead of static enumerations.

Thanks to this change the amount of code requried to support a SoC can
be greatly reduced and the code made more readable.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Tomasz Figa 2012-10-11 10:11:09 +02:00 committed by Linus Walleij
parent 62f14c0ef5
commit 40ba6227ae
3 changed files with 62 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
drivers/pinctrl/pinctrl-exynos.c
View File

@ -484,51 +484,51 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
/* pin banks of exynos4210 pin-controller 0 */
static struct samsung_pin_bank exynos4210_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0"),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1"),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb"),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0"),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1"),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0"),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1"),
EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0"),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1"),
EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2"),
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3"),
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4"),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0"),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1"),
EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2"),
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3"),
};
/* pin banks of exynos4210 pin-controller 1 */
static struct samsung_pin_bank exynos4210_pin_banks1[] = {
EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0"),
EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1"),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0"),
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1"),
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2"),
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3"),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0"),
EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1"),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2"),
EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
EXYNOS_PIN_BANK_EINTN(8, 0xC00, "gpx0"),
EXYNOS_PIN_BANK_EINTN(8, 0xC20, "gpx1"),
EXYNOS_PIN_BANK_EINTN(8, 0xC40, "gpx2"),
EXYNOS_PIN_BANK_EINTN(8, 0xC60, "gpx3"),
};
/* pin banks of exynos4210 pin-controller 2 */
static struct samsung_pin_bank exynos4210_pin_banks2[] = {
EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
};
/*
@ -540,9 +540,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 0 data */
.pin_banks = exynos4210_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
.base = EXYNOS4210_GPIO_A0_START,
.nr_pins = EXYNOS4210_GPIOA_NR_PINS,
.nr_gint = EXYNOS4210_GPIOA_NR_GINT,
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
@ -553,9 +550,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 1 data */
.pin_banks = exynos4210_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
.base = EXYNOS4210_GPIOA_NR_PINS,
.nr_pins = EXYNOS4210_GPIOB_NR_PINS,
.nr_gint = EXYNOS4210_GPIOB_NR_GINT,
.nr_wint = 32,
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
@ -571,9 +565,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 2 data */
.pin_banks = exynos4210_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
.base = EXYNOS4210_GPIOA_NR_PINS +
EXYNOS4210_GPIOB_NR_PINS,
.nr_pins = EXYNOS4210_GPIOC_NR_PINS,
.label = "exynos4210-gpio-ctrl2",
},
};

11
drivers/pinctrl/pinctrl-exynos.h
View File

@ -165,11 +165,10 @@ enum exynos4210_gpio_xc_start {
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
{ \
.pctl_offset = reg, \
.pin_base = (__gpio##_START), \
.nr_pins = (__gpio##_NR), \
.nr_pins = pins, \
.func_width = 4, \
.pud_width = 2, \
.drv_width = 2, \
@ -179,18 +178,16 @@ enum exynos4210_gpio_xc_start {
.name = id \
}
#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \
#define EXYNOS_PIN_BANK_EINTG(pins, reg, id) \
{ \
.pctl_offset = reg, \
.pin_base = (__gpio##_START), \
.nr_pins = (__gpio##_NR), \
.nr_pins = pins, \
.func_width = 4, \
.pud_width = 2, \
.drv_width = 2, \
.conpdn_width = 2, \
.pudpdn_width = 2, \
.eint_type = EINT_TYPE_GPIO, \
.irq_base = (__gpio##_IRQ), \
.name = id \
}

22
drivers/pinctrl/pinctrl-samsung.c
View File

@ -46,6 +46,8 @@ struct pin_config {
{ "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
};
static unsigned int pin_base = 0;
/* check if the selector is a valid pin group selector */
static int samsung_get_group_count(struct pinctrl_dev *pctldev)
{
@ -792,6 +794,9 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
int id;
const struct of_device_id *match;
const struct device_node *node = pdev->dev.of_node;
struct samsung_pin_ctrl *ctrl;
struct samsung_pin_bank *bank;
int i;
id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
if (id < 0) {
@ -799,7 +804,22 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
return NULL;
}
match = of_match_node(samsung_pinctrl_dt_match, node);
return (struct samsung_pin_ctrl *)match->data + id;
ctrl = (struct samsung_pin_ctrl *)match->data + id;
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
if (bank->eint_type == EINT_TYPE_GPIO) {
bank->irq_base = ctrl->nr_gint;
ctrl->nr_gint += bank->nr_pins;
}
}
ctrl->base = pin_base;
pin_base += ctrl->nr_pins;
return ctrl;
}
static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)