Merge OMAP5 DSS changes to omapdss
This series adds basic OMAP5 DSS functionality, mainly related to DSS core, DPI and DSI. * omap5-dss: OMAPDSS: DSI: make OMAP2_DSS_DSI depend on ARCH_OMAP5 OMAPDSS: DSI: Add code to disable PHY DCC OMAPDSS: DSI: Add new linebuffer size for OMAP5 OMAPDSS: DSI: Add FEAT_DSI_PLL_REFSEL OMAPDSS: DSI: Add FEAT_DSI_PLL_SELFREQDCO OMAPDSS: Add support for DPI source selection OMAPDSS: move dss feats to the end of dss.c OMAPDSS: Add basic omap5 features to dss and dispc OMAPDSS: DSI: improve DSI clock calcs for DISPC
This commit is contained in:
Tomi Valkeinen
commit
406f7b8baa
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@ -84,7 +84,7 @@ config OMAP2_DSS_SDI
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config OMAP2_DSS_DSI
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bool "DSI support"
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depends on ARCH_OMAP3 || ARCH_OMAP4
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depends on ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
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default n
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help
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MIPI DSI (Display Serial Interface) support.
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@ -3829,6 +3829,8 @@ static int __init dispc_init_features(struct device *dev)
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src = &omap34xx_rev3_0_dispc_feats;
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} else if (cpu_is_omap44xx()) {
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src = &omap44xx_dispc_feats;
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} else if (soc_is_omap54xx()) {
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src = &omap44xx_dispc_feats;
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} else {
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return -ENODEV;
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}
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@ -203,6 +203,10 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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if (r)
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goto err_get_dispc;
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r = dss_dpi_select_source(dssdev->channel);
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if (r)
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goto err_src_sel;
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if (dpi_use_dsi_pll(dssdev)) {
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r = dsi_runtime_get(dpi.dsidev);
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if (r)
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@ -237,6 +241,7 @@ err_dsi_pll_init:
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if (dpi_use_dsi_pll(dssdev))
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dsi_runtime_put(dpi.dsidev);
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err_get_dsi:
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err_src_sel:
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dispc_runtime_put();
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err_get_dispc:
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if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
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@ -1454,26 +1454,17 @@ found:
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}
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static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
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unsigned long req_clk, struct dsi_clock_info *cinfo)
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unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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struct dsi_clock_info cur, best;
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unsigned long dss_sys_clk, max_dss_fck, max_dsi_fck;
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unsigned long req_clkin4ddr;
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DSSDBG("dsi_pll_calc_ddrfreq\n");
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dss_sys_clk = clk_get_rate(dsi->sys_clk);
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
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memset(&best, 0, sizeof(best));
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memset(&cur, 0, sizeof(cur));
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cur.clkin = dss_sys_clk;
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req_clkin4ddr = req_clk * 4;
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cur.clkin = clk_get_rate(dsi->sys_clk);
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for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
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cur.fint = cur.clkin / cur.regn;
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@ -1503,18 +1494,107 @@ static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
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}
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}
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found:
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best.regm_dispc = DIV_ROUND_UP(best.clkin4ddr, max_dss_fck);
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best.dsi_pll_hsdiv_dispc_clk = best.clkin4ddr / best.regm_dispc;
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best.regm_dsi = DIV_ROUND_UP(best.clkin4ddr, max_dsi_fck);
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best.dsi_pll_hsdiv_dsi_clk = best.clkin4ddr / best.regm_dsi;
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if (cinfo)
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*cinfo = best;
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return 0;
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}
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static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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unsigned long max_dsi_fck;
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max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
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cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
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cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
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}
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static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
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unsigned long req_pck, struct dsi_clock_info *cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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unsigned regm_dispc, best_regm_dispc;
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unsigned long dispc_clk, best_dispc_clk;
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int min_fck_per_pck;
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unsigned long max_dss_fck;
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struct dispc_clock_info best_dispc;
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bool match;
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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min_fck_per_pck = 0;
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}
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retry:
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best_regm_dispc = 0;
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best_dispc_clk = 0;
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memset(&best_dispc, 0, sizeof(best_dispc));
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match = false;
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for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
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struct dispc_clock_info cur_dispc;
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dispc_clk = cinfo->clkin4ddr / regm_dispc;
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/* this will narrow down the search a bit,
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* but still give pixclocks below what was
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* requested */
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if (dispc_clk < req_pck)
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break;
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if (dispc_clk > max_dss_fck)
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continue;
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if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
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continue;
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match = true;
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dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
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if (abs(cur_dispc.pck - req_pck) <
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abs(best_dispc.pck - req_pck)) {
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best_regm_dispc = regm_dispc;
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best_dispc_clk = dispc_clk;
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best_dispc = cur_dispc;
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if (cur_dispc.pck == req_pck)
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goto found;
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}
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}
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if (!match) {
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if (min_fck_per_pck) {
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DSSERR("Could not find suitable clock settings.\n"
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"Turning FCK/PCK constraint off and"
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"trying again.\n");
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min_fck_per_pck = 0;
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goto retry;
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}
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DSSERR("Could not find suitable clock settings.\n");
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return -EINVAL;
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}
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found:
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cinfo->regm_dispc = best_regm_dispc;
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cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
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*dispc_cinfo = best_dispc;
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return 0;
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}
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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@ -1591,21 +1671,27 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev,
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BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
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l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
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if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
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f = cinfo->fint < 1000000 ? 0x3 :
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cinfo->fint < 1250000 ? 0x4 :
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cinfo->fint < 1500000 ? 0x5 :
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cinfo->fint < 1750000 ? 0x6 :
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0x7;
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l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
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} else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
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f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
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l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
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}
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l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
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if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
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l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
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l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
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l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
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l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
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if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
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l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
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dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
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REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
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@ -2069,6 +2155,8 @@ static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
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return 1194 * 3; /* 1194x24 bits */
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case 6:
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return 1365 * 3; /* 1365x24 bits */
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case 7:
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return 1920 * 3; /* 1920x24 bits */
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default:
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BUG();
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return 0;
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@ -2204,6 +2292,13 @@ static void dsi_cio_timings(struct platform_device *dsidev)
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r = FLD_MOD(r, tlpx_half, 22, 16);
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r = FLD_MOD(r, tclk_trail, 15, 8);
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r = FLD_MOD(r, tclk_zero, 7, 0);
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if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
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r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
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r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
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r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
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}
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dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
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r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
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@ -4188,33 +4283,35 @@ int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
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mutex_lock(&dsi->lock);
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r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk, &cinfo);
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/* Calculate PLL output clock */
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r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
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if (r)
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goto err;
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/* Calculate PLL's DSI clock */
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dsi_pll_calc_dsi_fck(dsidev, &cinfo);
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/* Calculate PLL's DISPC clock and pck & lck divs */
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pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
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DSSDBG("finding dispc dividers for pck %lu\n", pck);
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r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
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if (r)
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goto err;
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/* Calculate LP clock */
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dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
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lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
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dssdev->clocks.dsi.regn = cinfo.regn;
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dssdev->clocks.dsi.regm = cinfo.regm;
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dssdev->clocks.dsi.regm_dispc = cinfo.regm_dispc;
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dssdev->clocks.dsi.regm_dsi = cinfo.regm_dsi;
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dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
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lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
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dssdev->clocks.dsi.lp_clk_div = lp_clk_div;
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/* pck = TxByteClkHS * datalanes * 8 / bitsperpixel */
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pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
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DSSDBG("finding dispc dividers for pck %lu\n", pck);
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dispc_find_clk_divs(pck, cinfo.dsi_pll_hsdiv_dispc_clk, &dispc_cinfo);
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dssdev->clocks.dispc.channel.lck_div = dispc_cinfo.lck_div;
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dssdev->clocks.dispc.channel.pck_div = dispc_cinfo.pck_div;
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dssdev->clocks.dispc.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
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dssdev->clocks.dispc.channel.lcd_clk_src =
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@ -69,6 +69,7 @@ struct dss_features {
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u8 fck_div_max;
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u8 dss_fck_multiplier;
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const char *clk_name;
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int (*dpi_select_source)(enum omap_channel channel);
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};
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static struct {
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@ -99,30 +100,6 @@ static const char * const dss_generic_clk_source_names[] = {
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[OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
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};
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static const struct dss_features omap24xx_dss_feats __initconst = {
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.fck_div_max = 16,
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.dss_fck_multiplier = 2,
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.clk_name = NULL,
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};
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static const struct dss_features omap34xx_dss_feats __initconst = {
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.fck_div_max = 16,
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.dss_fck_multiplier = 2,
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.clk_name = "dpll4_m4_ck",
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};
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static const struct dss_features omap3630_dss_feats __initconst = {
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.fck_div_max = 32,
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.dss_fck_multiplier = 1,
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.clk_name = "dpll4_m4_ck",
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};
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static const struct dss_features omap44xx_dss_feats __initconst = {
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.fck_div_max = 32,
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.dss_fck_multiplier = 1,
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.clk_name = "dpll_per_m5x2_ck",
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};
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static inline void dss_write_reg(const struct dss_reg idx, u32 val)
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{
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__raw_writel(val, dss.base + idx.idx);
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@ -647,6 +624,65 @@ enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
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return REG_GET(DSS_CONTROL, 15, 15);
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}
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static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
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{
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if (channel != OMAP_DSS_CHANNEL_LCD)
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return -EINVAL;
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return 0;
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}
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static int dss_dpi_select_source_omap4(enum omap_channel channel)
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{
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int val;
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD2:
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val = 0;
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break;
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case OMAP_DSS_CHANNEL_DIGIT:
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val = 1;
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break;
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default:
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return -EINVAL;
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}
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REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
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return 0;
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}
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static int dss_dpi_select_source_omap5(enum omap_channel channel)
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{
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int val;
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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val = 1;
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break;
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case OMAP_DSS_CHANNEL_LCD2:
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val = 2;
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break;
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case OMAP_DSS_CHANNEL_LCD3:
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val = 3;
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break;
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case OMAP_DSS_CHANNEL_DIGIT:
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val = 0;
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break;
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default:
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return -EINVAL;
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}
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REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
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|
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return 0;
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}
|
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|
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int dss_dpi_select_source(enum omap_channel channel)
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{
|
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return dss.feat->dpi_select_source(channel);
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}
|
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|
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static int dss_get_clocks(void)
|
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{
|
||||
struct clk *clk;
|
||||
|
|
@ -721,6 +757,41 @@ void dss_debug_dump_clocks(struct seq_file *s)
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}
|
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#endif
|
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|
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static const struct dss_features omap24xx_dss_feats __initconst = {
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.fck_div_max = 16,
|
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.dss_fck_multiplier = 2,
|
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.clk_name = NULL,
|
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.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
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};
|
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|
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static const struct dss_features omap34xx_dss_feats __initconst = {
|
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.fck_div_max = 16,
|
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.dss_fck_multiplier = 2,
|
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.clk_name = "dpll4_m4_ck",
|
||||
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
||||
};
|
||||
|
||||
static const struct dss_features omap3630_dss_feats __initconst = {
|
||||
.fck_div_max = 32,
|
||||
.dss_fck_multiplier = 1,
|
||||
.clk_name = "dpll4_m4_ck",
|
||||
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
|
||||
};
|
||||
|
||||
static const struct dss_features omap44xx_dss_feats __initconst = {
|
||||
.fck_div_max = 32,
|
||||
.dss_fck_multiplier = 1,
|
||||
.clk_name = "dpll_per_m5x2_ck",
|
||||
.dpi_select_source = &dss_dpi_select_source_omap4,
|
||||
};
|
||||
|
||||
static const struct dss_features omap54xx_dss_feats __initconst = {
|
||||
.fck_div_max = 64,
|
||||
.dss_fck_multiplier = 1,
|
||||
.clk_name = "dpll_per_h12x2_ck",
|
||||
.dpi_select_source = &dss_dpi_select_source_omap5,
|
||||
};
|
||||
|
||||
static int __init dss_init_features(struct device *dev)
|
||||
{
|
||||
const struct dss_features *src;
|
||||
|
|
@ -740,6 +811,8 @@ static int __init dss_init_features(struct device *dev)
|
|||
src = &omap3630_dss_feats;
|
||||
else if (cpu_is_omap44xx())
|
||||
src = &omap44xx_dss_feats;
|
||||
else if (soc_is_omap54xx())
|
||||
src = &omap54xx_dss_feats;
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
|
|
|
|||
|
|
@ -280,6 +280,7 @@ void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
|
|||
int dss_init_platform_driver(void) __init;
|
||||
void dss_uninit_platform_driver(void);
|
||||
|
||||
int dss_dpi_select_source(enum omap_channel channel);
|
||||
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
|
||||
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
|
||||
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
|
||||
|
|
|
|||
|
|
@ -106,6 +106,21 @@ static const struct dss_reg_field omap4_dss_reg_fields[] = {
|
|||
[FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
|
||||
};
|
||||
|
||||
static const struct dss_reg_field omap5_dss_reg_fields[] = {
|
||||
[FEAT_REG_FIRHINC] = { 12, 0 },
|
||||
[FEAT_REG_FIRVINC] = { 28, 16 },
|
||||
[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
|
||||
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
|
||||
[FEAT_REG_FIFOSIZE] = { 15, 0 },
|
||||
[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
|
||||
[FEAT_REG_VERTICALACCU] = { 26, 16 },
|
||||
[FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
|
||||
[FEAT_REG_DSIPLL_REGN] = { 8, 1 },
|
||||
[FEAT_REG_DSIPLL_REGM] = { 20, 9 },
|
||||
[FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
|
||||
[FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
|
||||
};
|
||||
|
||||
static const enum omap_display_type omap2_dss_supported_displays[] = {
|
||||
/* OMAP_DSS_CHANNEL_LCD */
|
||||
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
|
||||
|
|
@ -144,6 +159,19 @@ static const enum omap_display_type omap4_dss_supported_displays[] = {
|
|||
OMAP_DISPLAY_TYPE_DSI,
|
||||
};
|
||||
|
||||
static const enum omap_display_type omap5_dss_supported_displays[] = {
|
||||
/* OMAP_DSS_CHANNEL_LCD */
|
||||
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
|
||||
OMAP_DISPLAY_TYPE_DSI,
|
||||
|
||||
/* OMAP_DSS_CHANNEL_DIGIT */
|
||||
OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
|
||||
|
||||
/* OMAP_DSS_CHANNEL_LCD2 */
|
||||
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
|
||||
OMAP_DISPLAY_TYPE_DSI,
|
||||
};
|
||||
|
||||
static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
|
||||
/* OMAP_DSS_GFX */
|
||||
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
|
||||
|
|
@ -298,6 +326,14 @@ static const char * const omap4_dss_clk_source_names[] = {
|
|||
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
|
||||
};
|
||||
|
||||
static const char * const omap5_dss_clk_source_names[] = {
|
||||
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
|
||||
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
|
||||
[OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
|
||||
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
|
||||
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
|
||||
};
|
||||
|
||||
static const struct dss_param_range omap2_dss_param_range[] = {
|
||||
[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
|
||||
[FEAT_PARAM_DSS_PCD] = { 2, 255 },
|
||||
|
|
@ -349,6 +385,22 @@ static const struct dss_param_range omap4_dss_param_range[] = {
|
|||
[FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
|
||||
};
|
||||
|
||||
static const struct dss_param_range omap5_dss_param_range[] = {
|
||||
[FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
|
||||
[FEAT_PARAM_DSS_PCD] = { 1, 255 },
|
||||
[FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
|
||||
[FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
|
||||
[FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
|
||||
[FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
|
||||
[FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
|
||||
[FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
|
||||
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
|
||||
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
|
||||
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
|
||||
[FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
|
||||
[FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
|
||||
};
|
||||
|
||||
static const enum dss_feat_id omap2_dss_feat_list[] = {
|
||||
FEAT_LCDENABLEPOL,
|
||||
FEAT_LCDENABLESIGNAL,
|
||||
|
|
@ -469,6 +521,28 @@ static const enum dss_feat_id omap4_dss_feat_list[] = {
|
|||
FEAT_BURST_2D,
|
||||
};
|
||||
|
||||
static const enum dss_feat_id omap5_dss_feat_list[] = {
|
||||
FEAT_MGR_LCD2,
|
||||
FEAT_CORE_CLK_DIV,
|
||||
FEAT_LCD_CLK_SRC,
|
||||
FEAT_DSI_DCS_CMD_CONFIG_VC,
|
||||
FEAT_DSI_VC_OCP_WIDTH,
|
||||
FEAT_DSI_GNQ,
|
||||
FEAT_HDMI_CTS_SWMODE,
|
||||
FEAT_HDMI_AUDIO_USE_MCLK,
|
||||
FEAT_HANDLE_UV_SEPARATE,
|
||||
FEAT_ATTR2,
|
||||
FEAT_CPR,
|
||||
FEAT_PRELOAD,
|
||||
FEAT_FIR_COEF_V,
|
||||
FEAT_ALPHA_FREE_ZORDER,
|
||||
FEAT_FIFO_MERGE,
|
||||
FEAT_BURST_2D,
|
||||
FEAT_DSI_PLL_SELFREQDCO,
|
||||
FEAT_DSI_PLL_REFSEL,
|
||||
FEAT_DSI_PHY_DCC,
|
||||
};
|
||||
|
||||
/* OMAP2 DSS Features */
|
||||
static const struct omap_dss_features omap2_dss_features = {
|
||||
.reg_fields = omap2_dss_reg_fields,
|
||||
|
|
@ -612,6 +686,26 @@ static const struct omap_dss_features omap4_dss_features = {
|
|||
.burst_size_unit = 16,
|
||||
};
|
||||
|
||||
/* OMAP5 DSS Features */
|
||||
static const struct omap_dss_features omap5_dss_features = {
|
||||
.reg_fields = omap5_dss_reg_fields,
|
||||
.num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
|
||||
|
||||
.features = omap5_dss_feat_list,
|
||||
.num_features = ARRAY_SIZE(omap5_dss_feat_list),
|
||||
|
||||
.num_mgrs = 3,
|
||||
.num_ovls = 4,
|
||||
.supported_displays = omap5_dss_supported_displays,
|
||||
.supported_color_modes = omap4_dss_supported_color_modes,
|
||||
.overlay_caps = omap4_dss_overlay_caps,
|
||||
.clksrc_names = omap5_dss_clk_source_names,
|
||||
.dss_params = omap5_dss_param_range,
|
||||
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
|
||||
.buffer_size_unit = 16,
|
||||
.burst_size_unit = 16,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_OMAP4_DSS_HDMI)
|
||||
/* HDMI OMAP4 Functions*/
|
||||
static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
|
||||
|
|
@ -754,6 +848,8 @@ void dss_features_init(void)
|
|||
omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
|
||||
else if (cpu_is_omap44xx())
|
||||
omap_current_dss_features = &omap4_dss_features;
|
||||
else if (soc_is_omap54xx())
|
||||
omap_current_dss_features = &omap5_dss_features;
|
||||
else
|
||||
DSSWARN("Unsupported OMAP version");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,6 +65,9 @@ enum dss_feat_id {
|
|||
/* An unknown HW bug causing the normal FIFO thresholds not to work */
|
||||
FEAT_OMAP3_DSI_FIFO_BUG,
|
||||
FEAT_BURST_2D,
|
||||
FEAT_DSI_PLL_SELFREQDCO,
|
||||
FEAT_DSI_PLL_REFSEL,
|
||||
FEAT_DSI_PHY_DCC,
|
||||
};
|
||||
|
||||
/* DSS register field id */
|
||||
|
|
|
|||
Reference in New Issue