ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain In case of AM33xx family of devices, there is no consistency between PWRSTCTRL & PWRSTST register offsers in PRM space, for example - PRM_XXX PWRSTCTRL PWRSTST ======================================= PRM_PER_MOD: 0x0C, 0x08 PRM_WKUP_MOD: 0x04, 0x08 PRM_MPU_MOD: 0x00, 0x04 PRM_DEVICE_MOD: NA, NA And also, there is no consistency between bit-offsets inside PWRSTCTRL & PWRSTST register, for example - PRM_XXX LOGICRET MEMON MEMRET ======================================= GFX_PWRCTRL: 2, 17, 6 PER_PWRCTRL: 3, 25, 29 MPU_PWRCTRL: 2, 18, 22 WKUP_PWRCTRL: 3, NA, NA This means, we need to maintain and pass on all this information in powerdomain handle; so adding fields for, - PWRSTCTRL/ST register offset - Logic retention state mask - mem_on/ret/pwrst/retst mask Currently, this fields is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support"; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Vaibhav Hiremath
Paul Walmsley
parent
f969a6dcec
commit
3f0ea7645a
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@ -115,6 +115,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
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obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
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# PRCM clockdomain control
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clockdomain-common += clockdomain.o
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@ -485,6 +485,7 @@ void __init am33xx_init_early(void)
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ti81xx_check_features();
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omap_common_init_early();
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am33xx_voltagedomains_init();
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am33xx_powerdomains_init();
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}
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#endif
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@ -67,9 +67,9 @@
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/*
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* Maximum number of clockdomains that can be associated with a powerdomain.
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* CORE powerdomain on OMAP4 is the worst case
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* PER powerdomain on AM33XX is the worst case
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*/
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#define PWRDM_MAX_CLKDMS 9
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#define PWRDM_MAX_CLKDMS 11
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/* XXX A completely arbitrary number. What is reasonable here? */
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#define PWRDM_TRANSITION_BAILOUT 100000
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@ -92,6 +92,15 @@ struct powerdomain;
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* @pwrdm_clkdms: Clockdomains in this powerdomain
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* @node: list_head linking all powerdomains
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* @voltdm_node: list_head linking all powerdomains in a voltagedomain
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* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
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* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
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* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
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* in @pwrstctrl_offs
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* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
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* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
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* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
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* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
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* in @pwrstctrl_offs
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* @state:
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* @state_counter:
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* @timer:
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@ -121,6 +130,14 @@ struct powerdomain {
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unsigned ret_logic_off_counter;
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unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
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const u8 pwrstctrl_offs;
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const u8 pwrstst_offs;
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const u32 logicretstate_mask;
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const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
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#ifdef CONFIG_PM_DEBUG
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s64 timer;
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s64 state_timer[PWRDM_MAX_PWRSTS];
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@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
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extern void omap242x_powerdomains_init(void);
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extern void omap243x_powerdomains_init(void);
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extern void omap3xxx_powerdomains_init(void);
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extern void am33xx_powerdomains_init(void);
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extern void omap44xx_powerdomains_init(void);
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extern struct pwrdm_ops omap2_pwrdm_operations;
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extern struct pwrdm_ops omap3_pwrdm_operations;
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extern struct pwrdm_ops am33xx_pwrdm_operations;
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extern struct pwrdm_ops omap4_pwrdm_operations;
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/* Common Internal functions used across OMAP rev's */
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@ -0,0 +1,229 @@
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/*
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* AM33XX Powerdomain control
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
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* <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <plat/prcm.h>
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#include "powerdomain.h"
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#include "prm33xx.h"
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#include "prm-regbits-33xx.h"
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static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= OMAP_POWERSTATE_MASK;
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v >>= OMAP_POWERSTATE_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= OMAP_POWERSTATEST_MASK;
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v >>= OMAP_POWERSTATEST_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
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v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
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{
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am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
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(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
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{
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am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
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AM33XX_LASTPOWERSTATEENTERED_MASK,
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pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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return 0;
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}
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static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
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{
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u32 m;
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m = pwrdm->logicretstate_mask;
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= AM33XX_LOGICSTATEST_MASK;
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v >>= AM33XX_LOGICSTATEST_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
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{
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u32 v, m;
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m = pwrdm->logicretstate_mask;
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = pwrdm->mem_on_mask[bank];
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = pwrdm->mem_ret_mask[bank];
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m, v;
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m = pwrdm->mem_pwrst_mask[bank];
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m, v;
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m = pwrdm->mem_retst_mask[bank];
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
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{
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u32 c = 0;
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/*
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* REVISIT: pwrdm_wait_transition() may be better implemented
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* via a callback and a periodic timer check -- how long do we expect
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* powerdomain transitions to take?
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*/
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/* XXX Is this udelay() value meaningful? */
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while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
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& OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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pr_err("powerdomain: %s: waited too long to complete transition\n",
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pwrdm->name);
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return -EAGAIN;
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}
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pr_debug("powerdomain: completed transition in %d loops\n", c);
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return 0;
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}
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struct pwrdm_ops am33xx_pwrdm_operations = {
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.pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
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.pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
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.pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
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.pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
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.pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
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.pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
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.pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
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.pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
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.pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
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.pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
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};
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@ -0,0 +1,185 @@
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/*
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* AM33XX Power domain data
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include "powerdomain.h"
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#include "prcm-common.h"
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#include "prm-regbits-33xx.h"
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#include "prm33xx.h"
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static struct powerdomain gfx_33xx_pwrdm = {
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.name = "gfx_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_GFX_MOD,
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.pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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.banks = 1,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
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.mem_on_mask = {
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[0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
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},
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.mem_ret_mask = {
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[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
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},
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.mem_pwrst_mask = {
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[0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
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},
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.mem_retst_mask = {
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[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
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},
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* gfx_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* gfx_mem */
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},
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};
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static struct powerdomain rtc_33xx_pwrdm = {
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.name = "rtc_pwrdm",
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.voltdm = { .name = "rtc" },
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.prcm_offs = AM33XX_PRM_RTC_MOD,
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.pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_ON,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
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};
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static struct powerdomain wkup_33xx_pwrdm = {
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.name = "wkup_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_WKUP_MOD,
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.pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_ON,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
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};
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static struct powerdomain per_33xx_pwrdm = {
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.name = "per_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_PER_MOD,
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.pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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.banks = 3,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
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.mem_on_mask = {
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[0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
|
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[1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_ret_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_pwrst_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
|
||||
},
|
||||
.mem_retst_mask = {
|
||||
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
||||
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
||||
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
||||
},
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* pruss_mem */
|
||||
[1] = PWRSTS_OFF_RET, /* per_mem */
|
||||
[2] = PWRSTS_OFF_RET, /* ram_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* pruss_mem */
|
||||
[1] = PWRSTS_ON, /* per_mem */
|
||||
[2] = PWRSTS_ON, /* ram_mem */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_33xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.voltdm = { .name = "mpu" },
|
||||
.prcm_offs = AM33XX_PRM_MPU_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.banks = 3,
|
||||
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
||||
.mem_on_mask = {
|
||||
[0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_ret_mask = {
|
||||
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_pwrst_mask = {
|
||||
[0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
|
||||
},
|
||||
.mem_retst_mask = {
|
||||
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
||||
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
||||
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
||||
},
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* mpu_l1 */
|
||||
[1] = PWRSTS_OFF_RET, /* mpu_l2 */
|
||||
[2] = PWRSTS_OFF_RET, /* mpu_ram */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* mpu_l1 */
|
||||
[1] = PWRSTS_ON, /* mpu_l2 */
|
||||
[2] = PWRSTS_ON, /* mpu_ram */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain cefuse_33xx_pwrdm = {
|
||||
.name = "cefuse_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = AM33XX_PRM_CEFUSE_MOD,
|
||||
.pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
|
||||
.pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct powerdomain *powerdomains_am33xx[] __initdata = {
|
||||
&gfx_33xx_pwrdm,
|
||||
&rtc_33xx_pwrdm,
|
||||
&wkup_33xx_pwrdm,
|
||||
&per_33xx_pwrdm,
|
||||
&mpu_33xx_pwrdm,
|
||||
&cefuse_33xx_pwrdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init am33xx_powerdomains_init(void)
|
||||
{
|
||||
pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_am33xx);
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
Reference in New Issue