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[PARISC] Abstract shift register left in .S 

Abstract existing shift register left macros as shift register
right are. This lends itself to a nice clean up of some #ifdef
blocks in entry.S

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Kyle McMartin 2006-08-13 22:17:19 -04:00 committed by Matthew Wilcox
parent f86e45131f
commit 3d73cf5e18
2 changed files with 8 additions and 17 deletions
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19
arch/parisc/kernel/entry.S
View File

@ -30,6 +30,7 @@
#include <asm/psw.h> #include <asm/psw.h>
#include <asm/cache.h> /* for L1_CACHE_SHIFT */
#include <asm/assembly.h> /* for LDREG/STREG defines */ #include <asm/assembly.h> /* for LDREG/STREG defines */
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/signal.h> #include <asm/signal.h>
@ -478,11 +479,7 @@
bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
copy \pmd,%r9 copy \pmd,%r9
#ifdef CONFIG_64BIT SHLREG %r9,PxD_VALUE_SHIFT,\pmd
shld %r9,PxD_VALUE_SHIFT,\pmd
#else
shlw %r9,PxD_VALUE_SHIFT,\pmd
#endif
EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
@ -970,11 +967,7 @@ intr_return:
/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
** irq_stat[] is defined using ____cacheline_aligned. ** irq_stat[] is defined using ____cacheline_aligned.
*/ */
#ifdef CONFIG_64BIT SHLREG %r1,L1_CACHE_SHIFT,%r20
shld %r1, 6, %r20
#else
shlw %r1, 5, %r20
#endif
add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
@ -2115,11 +2108,7 @@ syscall_check_bh:
ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */ ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */ /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
#ifdef CONFIG_64BIT SHLREG %r26,L1_CACHE_SHIFT,%r20
shld %r26, 6, %r20
#else
shlw %r26, 5, %r20
#endif
add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */

6
include/asm-parisc/assembly.h
View File

@ -29,7 +29,8 @@
#define LDREGX ldd,s #define LDREGX ldd,s
#define LDREGM ldd,mb #define LDREGM ldd,mb
#define STREGM std,ma #define STREGM std,ma
#define SHRREG shrd #define SHRREG shrd
#define SHLREG shld
#define RP_OFFSET 16 #define RP_OFFSET 16
#define FRAME_SIZE 128 #define FRAME_SIZE 128
#define CALLEE_REG_FRAME_SIZE 144 #define CALLEE_REG_FRAME_SIZE 144
@ -39,7 +40,8 @@
#define LDREGX ldwx,s #define LDREGX ldwx,s
#define LDREGM ldwm #define LDREGM ldwm
#define STREGM stwm #define STREGM stwm
#define SHRREG shr #define SHRREG shr
#define SHLREG shlw
#define RP_OFFSET 20 #define RP_OFFSET 20
#define FRAME_SIZE 64 #define FRAME_SIZE 64
#define CALLEE_REG_FRAME_SIZE 128 #define CALLEE_REG_FRAME_SIZE 128